dct.map.qmsg

8x8DCT verilog code 一次輸入8個點

{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "show3\[0\] DCT_1d_8b.v(19) " "Warning (10034): Output port \"show3\[0\]\" at DCT_1d_8b.v(19) has no driver" {  } { { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "B4DM.v 1 1 " "Warning: Using design file B4DM.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 B4DM " "Info: Found entity 1: B4DM" {  } { { "B4DM.v" "" { Text "D:/verilog/dct/DCT/B4DM.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "B4DM DCT_1d_8b:DCT_1d_8b\|B4DM:B4DM0 " "Info: Elaborating entity \"B4DM\" for hierarchy \"DCT_1d_8b:DCT_1d_8b\|B4DM:B4DM0\"" {  } { { "DCT_1d_8b.v" "B4DM0" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 62 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "DCT_1d_13bS.v 1 1 " "Warning: Using design file DCT_1d_13bS.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 DCT_1d_13bS " "Info: Found entity 1: DCT_1d_13bS" {  } { { "DCT_1d_13bS.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_13bS.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DCT_1d_13bS DCT_1d_13bS:DCT_1d_13bS " "Info: Elaborating entity \"DCT_1d_13bS\" for hierarchy \"DCT_1d_13bS:DCT_1d_13bS\"" {  } { { "DCT.v" "DCT_1d_13bS" { Text "D:/verilog/dct/DCT/DCT.v" 34 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "B4DM2.v 1 1 " "Warning: Using design file B4DM2.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 B4DM2 " "Info: Found entity 1: B4DM2" {  } { { "B4DM2.v" "" { Text "D:/verilog/dct/DCT/B4DM2.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "B4DM2 DCT_1d_13bS:DCT_1d_13bS\|B4DM2:B4DM20 " "Info: Elaborating entity \"B4DM2\" for hierarchy \"DCT_1d_13bS:DCT_1d_13bS\|B4DM2:B4DM20\"" {  } { { "DCT_1d_13bS.v" "B4DM20" { Text "D:/verilog/dct/DCT/DCT_1d_13bS.v" 53 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[2\]\[0\]\[12\] data_in GND " "Warning: Reduced register \"F\[2\]\[0\]\[12\]\" with stuck data_in port to stuck value GND" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[2\]\[0\]\[11\] data_in GND " "Warning: Reduced register \"F\[2\]\[0\]\[11\]\" with stuck data_in port to stuck value GND" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[1\]\[0\]\[12\] data_in GND " "Warning: Reduced register \"F\[1\]\[0\]\[12\]\" with stuck data_in port to stuck value GND" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[1\]\[0\]\[11\] data_in GND " "Warning: Reduced register \"F\[1\]\[0\]\[11\]\" with stuck data_in port to stuck value GND" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[0\]\[0\]\[12\] data_in GND " "Warning: Reduced register \"F\[0\]\[0\]\[12\]\" with stuck data_in port to stuck value GND" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[0\]\[0\]\[11\] data_in GND " "Warning: Reduced register \"F\[0\]\[0\]\[11\]\" with stuck data_in port to stuck value GND" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[3\]\[0\]\[11\] data_in GND " "Warning: Reduced register \"F\[3\]\[0\]\[11\]\" with stuck data_in port to stuck value GND" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[3\]\[0\]\[12\] data_in GND " "Warning: Reduced register \"F\[3\]\[0\]\[12\]\" with stuck data_in port to stuck value GND" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[4\]\[0\]\[11\] data_in GND " "Warning: Reduced register \"F\[4\]\[0\]\[11\]\" with stuck data_in port to stuck value GND" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[4\]\[0\]\[12\] data_in GND " "Warning: Reduced register \"F\[4\]\[0\]\[12\]\" with stuck data_in port to stuck value GND" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[5\]\[0\]\[11\] data_in GND " "Warning: Reduced register \"F\[5\]\[0\]\[11\]\" with stuck data_in port to stuck value GND" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[5\]\[0\]\[12\] data_in GND " "Warning: Reduced register \"F\[5\]\[0\]\[12\]\" with stuck data_in port to stuck value GND" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[6\]\[0\]\[11\] data_in GND " "Warning: Reduced register \"F\[6\]\[0\]\[11\]\" with stuck data_in port to stuck value GND" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[6\]\[0\]\[12\] data_in GND " "Warning: Reduced register \"F\[6\]\[0\]\[12\]\" with stuck data_in port to stuck value GND" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[7\]\[0\]\[11\] data_in GND " "Warning: Reduced register \"F\[7\]\[0\]\[11\]\" with stuck data_in port to stuck value GND" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[7\]\[0\]\[12\] data_in GND " "Warning: Reduced register \"F\[7\]\[0\]\[12\]\" with stuck data_in port to stuck value GND" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "F\[1\]\[7\]\[11\] F\[1\]\[7\]\[12\] " "Info: Duplicate register \"F\[1\]\[7\]\[11\]\" merged to single register \"F\[1\]\[7\]\[12\]\"" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "F\[0\]\[7\]\[11\] F\[0\]\[7\]\[12\] " "Info: Duplicate register \"F\[0\]\[7\]\[11\]\" merged to single register \"F\[0\]\[7\]\[12\]\"" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "F\[2\]\[7\]\[12\] F\[2\]\[7\]\[11\] " "Info: Duplicate register \"F\[2\]\[7\]\[12\]\" merged to single register \"F\[2\]\[7\]\[11\]\"" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "F\[3\]\[7\]\[12\] F\[3\]\[7\]\[11\] " "Info: Duplicate register \"F\[3\]\[7\]\[12\]\" merged to single register \"F\[3\]\[7\]\[11\]\"" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "F\[4\]\[7\]\[12\] F\[4\]\[7\]\[11\] " "Info: Duplicate register \"F\[4\]\[7\]\[12\]\" merged to single register \"F\[4\]\[7\]\[11\]\"" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "F\[5\]\[7\]\[12\] F\[5\]\[7\]\[11\] " "Info: Duplicate register \"F\[5\]\[7\]\[12\]\" merged to single register \"F\[5\]\[7\]\[11\]\"" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "F\[6\]\[7\]\[12\] F\[6\]\[7\]\[11\] " "Info: Duplicate register \"F\[6\]\[7\]\[12\]\" merged to single register \"F\[6\]\[7\]\[11\]\"" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "F\[7\]\[7\]\[12\] F\[7\]\[7\]\[11\] " "Info: Duplicate register \"F\[7\]\[7\]\[12\]\" merged to single register \"F\[7\]\[7\]\[11\]\"" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "F0_S\[11\] GND " "Warning: Pin \"F0_S\[11\]\" stuck at GND" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 16 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "F0_S\[12\] GND " "Warning: Pin \"F0_S\[12\]\" stuck at GND" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 16 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "3512 " "Info: Implemented 3512 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "66 " "Info: Implemented 66 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "249 " "Info: Implemented 249 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "3197 " "Info: Implemented 3197 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 71 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 71 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "148 " "Info: Allocated 148 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 12 16:42:49 2008 " "Info: Processing ended: Thu Jun 12 16:42:49 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}