dct.hif

8x8DCT verilog code 一次輸入8個點

DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b95
-1
3
q_b94
-1
3
q_b93
-1
3
q_b92
-1
3
q_b91
-1
3
q_b90
-1
3
q_b9
-1
3
q_b89
-1
3
q_b88
-1
3
q_b87
-1
3
q_b86
-1
3
q_b85
-1
3
q_b84
-1
3
q_b83
-1
3
q_b82
-1
3
q_b81
-1
3
q_b80
-1
3
q_b8
-1
3
q_b79
-1
3
q_b78
-1
3
q_b77
-1
3
q_b76
-1
3
q_b75
-1
3
q_b74
-1
3
q_b73
-1
3
q_b72
-1
3
q_b71
-1
3
q_b70
-1
3
q_b7
-1
3
q_b69
-1
3
q_b68
-1
3
q_b67
-1
3
q_b66
-1
3
q_b65
-1
3
q_b64
-1
3
q_b63
-1
3
q_b62
-1
3
q_b61
-1
3
q_b60
-1
3
q_b6
-1
3
q_b59
-1
3
q_b58
-1
3
q_b57
-1
3
q_b56
-1
3
q_b55
-1
3
q_b54
-1
3
q_b53
-1
3
q_b52
-1
3
q_b51
-1
3
q_b50
-1
3
q_b5
-1
3
q_b49
-1
3
q_b48
-1
3
q_b47
-1
3
q_b46
-1
3
q_b45
-1
3
q_b44
-1
3
q_b43
-1
3
q_b42
-1
3
q_b41
-1
3
q_b40
-1
3
q_b4
-1
3
q_b39
-1
3
q_b38
-1
3
q_b37
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a95
-1
3
data_a94
-1
3
data_a93
-1
3
data_a92
-1
3
data_a91
-1
3
data_a90
-1
3
data_a9
-1
3
data_a89
-1
3
data_a88
-1
3
data_a87
-1
3
data_a86
-1
3
data_a85
-1
3
data_a84
-1
3
data_a83
-1
3
data_a82
-1
3
data_a81
-1
3
data_a80
-1
3
data_a8
-1
3
data_a79
-1
3
data_a78
-1
3
data_a77
-1
3
data_a76
-1
3
data_a75
-1
3
data_a74
-1
3
data_a73
-1
3
data_a72
-1
3
data_a71
-1
3
data_a70
-1
3
data_a7
-1
3
data_a69
-1
3
data_a68
-1
3
data_a67
-1
3
data_a66
-1
3
data_a65
-1
3
data_a64
-1
3
data_a63
-1
3
data_a62
-1
3
data_a61
-1
3
data_a60
-1
3
data_a6
-1
3
data_a59
-1
3
data_a58
-1
3
data_a57
-1
3
data_a56
-1
3
data_a55
-1
3
data_a54
-1
3
data_a53
-1
3
data_a52
-1
3
data_a51
-1
3
data_a50
-1
3
data_a5
-1
3
data_a49
-1
3
data_a48
-1
3
data_a47
-1
3
data_a46
-1
3
data_a45
-1
3
data_a44
-1
3
data_a43
-1
3
data_a42
-1
3
data_a41
-1
3
data_a40
-1
3
data_a4
-1
3
data_a39
-1
3
data_a38
-1
3
data_a37
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
DCT_1d_8b
# storage
db|DCT.(1).cnf
db|DCT.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
DCT_1d_8b.v
69b1d4d875c0abcc1b21e499761907c
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
n
8
PARAMETER_SIGNED_DEC
DEF
}
# hierarchies {
DCT_1d_8b:DCT_1d_8b
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
B4DM
# storage
db|DCT.(2).cnf
db|DCT.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
B4DM.v
e6488591fc641529dc9b39127d3a5830
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
n
8
PARAMETER_SIGNED_DEC
DEF
}
# hierarchies {
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM0
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM1
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM2
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM3
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM4
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM5
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM6
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM7
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM8
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM10
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM11
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM12
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM13
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM14
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM15
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM16
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM17
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM18
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM19
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM20
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM21
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM22
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM23
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM24
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM25
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM26
DCT_1d_8b:DCT_1d_8b|B4DM:B4DM27
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
DCT_1d_13bS
# storage
db|DCT.(5).cnf
db|DCT.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
DCT_1d_13bS.v
5f7dc203fa933ba5a350f0e73ace77
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
n
13
PARAMETER_SIGNED_DEC
DEF
}
# hierarchies {
DCT_1d_13bS:DCT_1d_13bS
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
B4DM2
# storage
db|DCT.(6).cnf
db|DCT.(6).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
B4DM2.v
6cf8c1edac30befdd602752dd4726b4
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
n
14
PARAMETER_SIGNED_DEC
DEF
}
# hierarchies {
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM20
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM21
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM22
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM23
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM24
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM25
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM26
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM27
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM28
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM29
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM210
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM211
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM212
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM213
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM214
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM215
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM216
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM217
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM218
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM219
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM220
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM221
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM222
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM223
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM224
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM225
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM226
DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM227
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
DCT
# storage
db|DCT.(0).cnf
db|DCT.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
DCT.v
4f35bedee9479081f7ba69f7b7f159ab
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
|
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# complete