dct.hif

8x8DCT verilog code 一次輸入8個點

Version 7.1 Build 156 04/30/2007 SJ Full Version
11
912
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
altsyncram
# storage
db|DCT.(3).cnf
db|DCT.(3).cnf
# case_insensitive
# source_file
c:|altera|71|quartus|libraries|megafunctions|altsyncram.tdf
b69478c2691550fb7f5ef3923da937a
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
96
PARAMETER_UNKNOWN
USR
WIDTHAD_A
3
PARAMETER_UNKNOWN
USR
NUMWORDS_A
8
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
96
PARAMETER_UNKNOWN
USR
WIDTHAD_B
3
PARAMETER_UNKNOWN
USR
NUMWORDS_B
8
PARAMETER_UNKNOWN
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_nmi1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b95
-1
3
q_b94
-1
3
q_b93
-1
3
q_b92
-1
3
q_b91
-1
3
q_b90
-1
3
q_b9
-1
3
q_b89
-1
3
q_b88
-1
3
q_b87
-1
3
q_b86
-1
3
q_b85
-1
3
q_b84
-1
3
q_b83
-1
3
q_b82
-1
3
q_b81
-1
3
q_b80
-1
3
q_b8
-1
3
q_b79
-1
3
q_b78
-1
3
q_b77
-1
3
q_b76
-1
3
q_b75
-1
3
q_b74
-1
3
q_b73
-1
3
q_b72
-1
3
q_b71
-1
3
q_b70
-1
3
q_b7
-1
3
q_b69
-1
3
q_b68
-1
3
q_b67
-1
3
q_b66
-1
3
q_b65
-1
3
q_b64
-1
3
q_b63
-1
3
q_b62
-1
3
q_b61
-1
3
q_b60
-1
3
q_b6
-1
3
q_b59
-1
3
q_b58
-1
3
q_b57
-1
3
q_b56
-1
3
q_b55
-1
3
q_b54
-1
3
q_b53
-1
3
q_b52
-1
3
q_b51
-1
3
q_b50
-1
3
q_b5
-1
3
q_b49
-1
3
q_b48
-1
3
q_b47
-1
3
q_b46
-1
3
q_b45
-1
3
q_b44
-1
3
q_b43
-1
3
q_b42
-1
3
q_b41
-1
3
q_b40
-1
3
q_b4
-1
3
q_b39
-1
3
q_b38
-1
3
q_b37
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a95
-1
3
data_a94
-1
3
data_a93
-1
3
data_a92
-1
3
data_a91
-1
3
data_a90
-1
3
data_a9
-1
3
data_a89
-1
3
data_a88
-1
3
data_a87
-1
3
data_a86
-1
3
data_a85
-1
3
data_a84
-1
3
data_a83
-1
3
data_a82
-1
3
data_a81
-1
3
data_a80
-1
3
data_a8
-1
3
data_a79
-1
3
data_a78
-1
3
data_a77
-1
3
data_a76
-1
3
data_a75
-1
3
data_a74
-1
3
data_a73
-1
3
data_a72
-1
3
data_a71
-1
3
data_a70
-1
3
data_a7
-1
3
data_a69
-1
3
data_a68
-1
3
data_a67
-1
3
data_a66
-1
3
data_a65
-1
3
data_a64
-1
3
data_a63
-1
3
data_a62
-1
3
data_a61
-1
3
data_a60
-1
3
data_a6
-1
3
data_a59
-1
3
data_a58
-1
3
data_a57
-1
3
data_a56
-1
3
data_a55
-1
3
data_a54
-1
3
data_a53
-1
3
data_a52
-1
3
data_a51
-1
3
data_a50
-1
3
data_a5
-1
3
data_a49
-1
3
data_a48
-1
3
data_a47
-1
3
data_a46
-1
3
data_a45
-1
3
data_a44
-1
3
data_a43
-1
3
data_a42
-1
3
data_a41
-1
3
data_a40
-1
3
data_a4
-1
3
data_a39
-1
3
data_a38
-1
3
data_a37
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
c:|altera|71|quartus|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
c:|altera|71|quartus|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
c:|altera|71|quartus|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
c:|altera|71|quartus|libraries|megafunctions|aglobal71.inc
80b63f71158cd1a01acf29ef94ccd6
c:|altera|71|quartus|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
c:|altera|71|quartus|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
c:|altera|71|quartus|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
c:|altera|71|quartus|libraries|megafunctions|altdpram.inc
99d442b5b66c88db4daf94d99c6e4e77
c:|altera|71|quartus|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
altsyncram_nmi1
# storage
db|DCT.(4).cnf
db|DCT.(4).cnf
# case_insensitive
# source_file
db|altsyncram_nmi1.tdf
e9198af3111fefee8ca26186958be78
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN