📄 prev_cmp_dct.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "iclk register c1\[1\]~reg0 register F1_r\[4\] 276.93 MHz 3.611 ns Internal " "Info: Clock \"iclk\" has Internal fmax of 276.93 MHz between source register \"c1\[1\]~reg0\" and destination register \"F1_r\[4\]\" (period= 3.611 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.396 ns + Longest register register " "Info: + Longest register to register delay is 3.396 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns c1\[1\]~reg0 1 REG LCFF_X37_Y15_N27 249 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X37_Y15_N27; Fanout = 249; REG Node = 'c1\[1\]~reg0'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { c1[1]~reg0 } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 55 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.201 ns) + CELL(0.437 ns) 1.638 ns Mux19~39 2 COMB LCCOMB_X40_Y19_N18 1 " "Info: 2: + IC(1.201 ns) + CELL(0.437 ns) = 1.638 ns; Loc. = LCCOMB_X40_Y19_N18; Fanout = 1; COMB Node = 'Mux19~39'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.638 ns" { c1[1]~reg0 Mux19~39 } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 67 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(0.150 ns) 2.034 ns Mux19~40 3 COMB LCCOMB_X40_Y19_N20 1 " "Info: 3: + IC(0.246 ns) + CELL(0.150 ns) = 2.034 ns; Loc. = LCCOMB_X40_Y19_N20; Fanout = 1; COMB Node = 'Mux19~40'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.396 ns" { Mux19~39 Mux19~40 } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 67 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.007 ns) + CELL(0.271 ns) 3.312 ns Mux19~41 4 COMB LCCOMB_X36_Y16_N0 1 " "Info: 4: + IC(1.007 ns) + CELL(0.271 ns) = 3.312 ns; Loc. = LCCOMB_X36_Y16_N0; Fanout = 1; COMB Node = 'Mux19~41'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.278 ns" { Mux19~40 Mux19~41 } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 67 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.396 ns F1_r\[4\] 5 REG LCFF_X36_Y16_N1 4 " "Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 3.396 ns; Loc. = LCFF_X36_Y16_N1; Fanout = 4; REG Node = 'F1_r\[4\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { Mux19~41 F1_r[4] } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 55 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.942 ns ( 27.74 % ) " "Info: Total cell delay = 0.942 ns ( 27.74 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.454 ns ( 72.26 % ) " "Info: Total interconnect delay = 2.454 ns ( 72.26 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.396 ns" { c1[1]~reg0 Mux19~39 Mux19~40 Mux19~41 F1_r[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.396 ns" { c1[1]~reg0 Mux19~39 Mux19~40 Mux19~41 F1_r[4] } { 0.000ns 1.201ns 0.246ns 1.007ns 0.000ns } { 0.000ns 0.437ns 0.150ns 0.271ns 0.084ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.001 ns - Smallest " "Info: - Smallest clock skew is -0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iclk destination 2.667 ns + Shortest register " "Info: + Shortest clock path from clock \"iclk\" to destination register is 2.667 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns iclk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'iclk'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { iclk } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns iclk~clkctrl 2 COMB CLKCTRL_G3 761 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 761; COMB Node = 'iclk~clkctrl'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { iclk iclk~clkctrl } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.013 ns) + CELL(0.537 ns) 2.667 ns F1_r\[4\] 3 REG LCFF_X36_Y16_N1 4 " "Info: 3: + IC(1.013 ns) + CELL(0.537 ns) = 2.667 ns; Loc. = LCFF_X36_Y16_N1; Fanout = 4; REG Node = 'F1_r\[4\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.550 ns" { iclk~clkctrl F1_r[4] } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 55 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.59 % ) " "Info: Total cell delay = 1.536 ns ( 57.59 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.131 ns ( 42.41 % ) " "Info: Total interconnect delay = 1.131 ns ( 42.41 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.667 ns" { iclk iclk~clkctrl F1_r[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.667 ns" { iclk iclk~combout iclk~clkctrl F1_r[4] } { 0.000ns 0.000ns 0.118ns 1.013ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iclk source 2.668 ns - Longest register " "Info: - Longest clock path from clock \"iclk\" to source register is 2.668 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns iclk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'iclk'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { iclk } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns iclk~clkctrl 2 COMB CLKCTRL_G3 761 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 761; COMB Node = 'iclk~clkctrl'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { iclk iclk~clkctrl } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.537 ns) 2.668 ns c1\[1\]~reg0 3 REG LCFF_X37_Y15_N27 249 " "Info: 3: + IC(1.014 ns) + CELL(0.537 ns) = 2.668 ns; Loc. = LCFF_X37_Y15_N27; Fanout = 249; REG Node = 'c1\[1\]~reg0'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.551 ns" { iclk~clkctrl c1[1]~reg0 } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 55 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.57 % ) " "Info: Total cell delay = 1.536 ns ( 57.57 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.132 ns ( 42.43 % ) " "Info: Total interconnect delay = 1.132 ns ( 42.43 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.668 ns" { iclk iclk~clkctrl c1[1]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.668 ns" { iclk iclk~combout iclk~clkctrl c1[1]~reg0 } { 0.000ns 0.000ns 0.118ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.667 ns" { iclk iclk~clkctrl F1_r[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.667 ns" { iclk iclk~combout iclk~clkctrl F1_r[4] } { 0.000ns 0.000ns 0.118ns 1.013ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.668 ns" { iclk iclk~clkctrl c1[1]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.668 ns" { iclk iclk~combout iclk~clkctrl c1[1]~reg0 } { 0.000ns 0.000ns 0.118ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" { } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 55 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 55 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.396 ns" { c1[1]~reg0 Mux19~39 Mux19~40 Mux19~41 F1_r[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.396 ns" { c1[1]~reg0 Mux19~39 Mux19~40 Mux19~41 F1_r[4] } { 0.000ns 1.201ns 0.246ns 1.007ns 0.000ns } { 0.000ns 0.437ns 0.150ns 0.271ns 0.084ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.667 ns" { iclk iclk~clkctrl F1_r[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.667 ns" { iclk iclk~combout iclk~clkctrl F1_r[4] } { 0.000ns 0.000ns 0.118ns 1.013ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.668 ns" { iclk iclk~clkctrl c1[1]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.668 ns" { iclk iclk~combout iclk~clkctrl c1[1]~reg0 } { 0.000ns 0.000ns 0.118ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "F\[2\]\[4\]\[9\] d3\[1\] iclk 16.416 ns register " "Info: tsu for register \"F\[2\]\[4\]\[9\]\" (data pin = \"d3\[1\]\", clock pin = \"iclk\") is 16.416 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "19.128 ns + Longest pin register " "Info: + Longest pin to register delay is 19.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.840 ns) 0.840 ns d3\[1\] 1 PIN PIN_C9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_C9; Fanout = 4; PIN Node = 'd3\[1\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { d3[1] } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.776 ns) + CELL(0.414 ns) 7.030 ns DCT_1d_8b:DCT_1d_8b\|s3\[1\]~15 2 COMB LCCOMB_X14_Y24_N2 2 " "Info: 2: + IC(5.776 ns) + CELL(0.414 ns) = 7.030 ns; Loc. = LCCOMB_X14_Y24_N2; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|s3\[1\]~15'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.190 ns" { d3[1] DCT_1d_8b:DCT_1d_8b|s3[1]~15 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 7.101 ns DCT_1d_8b:DCT_1d_8b\|s3\[2\]~17 3 COMB LCCOMB_X14_Y24_N4 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 7.101 ns; Loc. = LCCOMB_X14_Y24_N4; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|s3\[2\]~17'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DCT_1d_8b:DCT_1d_8b|s3[1]~15 DCT_1d_8b:DCT_1d_8b|s3[2]~17 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 7.172 ns DCT_1d_8b:DCT_1d_8b\|s3\[3\]~19 4 COMB LCCOMB_X14_Y24_N6 2 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 7.172 ns; Loc. = LCCOMB_X14_Y24_N6; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|s3\[3\]~19'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DCT_1d_8b:DCT_1d_8b|s3[2]~17 DCT_1d_8b:DCT_1d_8b|s3[3]~19 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 7.582 ns DCT_1d_8b:DCT_1d_8b\|s3\[4\]~20 5 COMB LCCOMB_X14_Y24_N8 8 " "Info: 5: + IC(0.000 ns) + CELL(0.410 ns) = 7.582 ns; Loc. = LCCOMB_X14_Y24_N8; Fanout = 8; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|s3\[4\]~20'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { DCT_1d_8b:DCT_1d_8b|s3[3]~19 DCT_1d_8b:DCT_1d_8b|s3[4]~20 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.814 ns) + CELL(0.393 ns) 10.789 ns DCT_1d_8b:DCT_1d_8b\|Add18~194 6 COMB LCCOMB_X34_Y24_N12 2 " "Info: 6: + IC(2.814 ns) + CELL(0.393 ns) = 10.789 ns; Loc. = LCCOMB_X34_Y24_N12; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|Add18~194'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.207 ns" { DCT_1d_8b:DCT_1d_8b|s3[4]~20 DCT_1d_8b:DCT_1d_8b|Add18~194 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 10.948 ns DCT_1d_8b:DCT_1d_8b\|Add18~196 7 COMB LCCOMB_X34_Y24_N14 2 " "Info: 7: + IC(0.000 ns) + CELL(0.159 ns) = 10.948 ns; Loc. = LCCOMB_X34_Y24_N14; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|Add18~196'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.159 ns" { DCT_1d_8b:DCT_1d_8b|Add18~194 DCT_1d_8b:DCT_1d_8b|Add18~196 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 11.019 ns DCT_1d_8b:DCT_1d_8b\|Add18~198 8 COMB LCCOMB_X34_Y24_N16 2 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 11.019 ns; Loc. = LCCOMB_X34_Y24_N16; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|Add18~198'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DCT_1d_8b:DCT_1d_8b|Add18~196 DCT_1d_8b:DCT_1d_8b|Add18~198 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 11.429 ns DCT_1d_8b:DCT_1d_8b\|Add18~199 9 COMB LCCOMB_X34_Y24_N18 4 " "Info: 9: + IC(0.000 ns) + CELL(0.410 ns) = 11.429 ns; Loc. = LCCOMB_X34_Y24_N18; Fanout = 4; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|Add18~199'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { DCT_1d_8b:DCT_1d_8b|Add18~198 DCT_1d_8b:DCT_1d_8b|Add18~199 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.264 ns) + CELL(0.393 ns) 13.086 ns DCT_1d_8b:DCT_1d_8b\|Add19~136 10 COMB LCCOMB_X35_Y21_N18 2 " "Info: 10: + IC(1.264 ns) + CELL(0.393 ns) = 13.086 ns; Loc. = LCCOMB_X35_Y21_N18; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|Add19~136'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.657 ns" { DCT_1d_8b:DCT_1d_8b|Add18~199 DCT_1d_8b:DCT_1d_8b|Add19~136 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 13.157 ns DCT_1d_8b:DCT_1d_8b\|Add19~138 11 COMB LCCOMB_X35_Y21_N20 2 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 13.157 ns; Loc. = LCCOMB_X35_Y21_N20; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|Add19~138'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DCT_1d_8b:DCT_1d_8b|Add19~136 DCT_1d_8b:DCT_1d_8b|Add19~138 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 13.567 ns DCT_1d_8b:DCT_1d_8b\|Add19~139 12 COMB LCCOMB_X35_Y21_N22 4 " "Info: 12: + IC(0.000 ns) + CELL(0.410 ns) = 13.567 ns; Loc. = LCCOMB_X35_Y21_N22; Fanout = 4; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|Add19~139'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { DCT_1d_8b:DCT_1d_8b|Add19~138 DCT_1d_8b:DCT_1d_8b|Add19~139 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.693 ns) + CELL(0.414 ns) 14.674 ns DCT_1d_8b:DCT_1d_8b\|Add45~130 13 COMB LCCOMB_X36_Y21_N18 2 " "Info: 13: + IC(0.693 ns) + CELL(0.414 ns) = 14.674 ns; Loc. = LCCOMB_X36_Y21_N18; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|Add45~130'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.107 ns" { DCT_1d_8b:DCT_1d_8b|Add19~139 DCT_1d_8b:DCT_1d_8b|Add45~130 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 161 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 14.745 ns DCT_1d_8b:DCT_1d_8b\|Add45~132 14 COMB LCCOMB_X36_Y21_N20 1 " "Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 14.745 ns; Loc. = LCCOMB_X36_Y21_N20; Fanout = 1; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|Add45~132'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DCT_1d_8b:DCT_1d_8b|Add45~130 DCT_1d_8b:DCT_1d_8b|Add45~132 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 161 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 15.155 ns DCT_1d_8b:DCT_1d_8b\|Add45~133 15 COMB LCCOMB_X36_Y21_N22 2 " "Info: 15: + IC(0.000 ns) + CELL(0.410 ns) = 15.155 ns; Loc. = LCCOMB_X36_Y21_N22; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|Add45~133'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { DCT_1d_8b:DCT_1d_8b|Add45~132 DCT_1d_8b:DCT_1d_8b|Add45~133 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 161 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.153 ns) + CELL(0.393 ns) 16.701 ns DCT_1d_8b:DCT_1d_8b\|Add46~147 16 COMB LCCOMB_X36_Y20_N24 1 " "Info: 16: + IC(1.153 ns) + CELL(0.393 ns) = 16.701 ns; Loc. = LCCOMB_X36_Y20_N24; Fanout = 1; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|Add46~147'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.546 ns" { DCT_1d_8b:DCT_1d_8b|Add45~133 DCT_1d_8b:DCT_1d_8b|Add46~147 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 161 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 17.111 ns DCT_1d_8b:DCT_1d_8b\|Add46~148 17 COMB LCCOMB_X36_Y20_N26 9 " "Info: 17: + IC(0.000 ns) + CELL(0.410 ns) = 17.111 ns; Loc. = LCCOMB_X36_Y20_N26; Fanout = 9; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|Add46~148'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { DCT_1d_8b:DCT_1d_8b|Add46~147 DCT_1d_8b:DCT_1d_8b|Add46~148 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 161 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.784 ns) + CELL(0.149 ns) 19.044 ns F\[2\]\[4\]\[9\]~feeder 18 COMB LCCOMB_X45_Y15_N4 1 " "Info: 18: + IC(1.784 ns) + CELL(0.149 ns) = 19.044 ns; Loc. = LCCOMB_X45_Y15_N4; Fanout = 1; COMB Node = 'F\[2\]\[4\]\[9\]~feeder'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.933 ns" { DCT_1d_8b:DCT_1d_8b|Add46~148 F[2][4][9]~feeder } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 19.128 ns F\[2\]\[4\]\[9\] 19 REG LCFF_X45_Y15_N5 1 " "Info: 19: + IC(0.000 ns) + CELL(0.084 ns) = 19.128 ns; Loc. = LCFF_X45_Y15_N5; Fanout = 1; REG Node = 'F\[2\]\[4\]\[9\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { F[2][4][9]~feeder F[2][4][9] } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.644 ns ( 29.51 % ) " "Info: Total cell delay = 5.644 ns ( 29.51 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.484 ns ( 70.49 % ) " "Info: Total interconnect delay = 13.484 ns ( 70.49 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "19.128 ns" { d3[1] DCT_1d_8b:DCT_1d_8b|s3[1]~15 DCT_1d_8b:DCT_1d_8b|s3[2]~17 DCT_1d_8b:DCT_1d_8b|s3[3]~19 DCT_1d_8b:DCT_1d_8b|s3[4]~20 DCT_1d_8b:DCT_1d_8b|Add18~194 DCT_1d_8b:DCT_1d_8b|Add18~196 DCT_1d_8b:DCT_1d_8b|Add18~198 DCT_1d_8b:DCT_1d_8b|Add18~199 DCT_1d_8b:DCT_1d_8b|Add19~136 DCT_1d_8b:DCT_1d_8b|Add19~138 DCT_1d_8b:DCT_1d_8b|Add19~139 DCT_1d_8b:DCT_1d_8b|Add45~130 DCT_1d_8b:DCT_1d_8b|Add45~132 DCT_1d_8b:DCT_1d_8b|Add45~133 DCT_1d_8b:DCT_1d_8b|Add46~147 DCT_1d_8b:DCT_1d_8b|Add46~148 F[2][4][9]~feeder F[2][4][9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "19.128 ns" { d3[1] d3[1]~combout DCT_1d_8b:DCT_1d_8b|s3[1]~15 DCT_1d_8b:DCT_1d_8b|s3[2]~17 DCT_1d_8b:DCT_1d_8b|s3[3]~19 DCT_1d_8b:DCT_1d_8b|s3[4]~20 DCT_1d_8b:DCT_1d_8b|Add18~194 DCT_1d_8b:DCT_1d_8b|Add18~196 DCT_1d_8b:DCT_1d_8b|Add18~198 DCT_1d_8b:DCT_1d_8b|Add18~199 DCT_1d_8b:DCT_1d_8b|Add19~136 DCT_1d_8b:DCT_1d_8b|Add19~138 DCT_1d_8b:DCT_1d_8b|Add19~139 DCT_1d_8b:DCT_1d_8b|Add45~130 DCT_1d_8b:DCT_1d_8b|Add45~132 DCT_1d_8b:DCT_1d_8b|Add45~133 DCT_1d_8b:DCT_1d_8b|Add46~147 DCT_1d_8b:DCT_1d_8b|Add46~148 F[2][4][9]~feeder F[2][4][9] } { 0.000ns 0.000ns 5.776ns 0.000ns 0.000ns 0.000ns 2.814ns 0.000ns 0.000ns 0.000ns 1.264ns 0.000ns 0.000ns 0.693ns 0.000ns 0.000ns 1.153ns 0.000ns 1.784ns 0.000ns } { 0.000ns 0.840ns 0.414ns 0.071ns 0.071ns 0.410ns 0.393ns 0.159ns 0.071ns 0.410ns 0.393ns 0.071ns 0.410ns 0.414ns 0.071ns 0.410ns 0.393ns 0.410ns 0.149ns 0.084ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iclk destination 2.676 ns - Shortest register " "Info: - Shortest clock path from clock \"iclk\" to destination register is 2.676 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns iclk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'iclk'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { iclk } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns iclk~clkctrl 2 COMB CLKCTRL_G3 761 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 761; COMB Node = 'iclk~clkctrl'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { iclk iclk~clkctrl } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.022 ns) + CELL(0.537 ns) 2.676 ns F\[2\]\[4\]\[9\] 3 REG LCFF_X45_Y15_N5 1 " "Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.676 ns; Loc. = LCFF_X45_Y15_N5; Fanout = 1; REG Node = 'F\[2\]\[4\]\[9\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.559 ns" { iclk~clkctrl F[2][4][9] } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.40 % ) " "Info: Total cell delay = 1.536 ns ( 57.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.140 ns ( 42.60 % ) " "Info: Total interconnect delay = 1.140 ns ( 42.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.676 ns" { iclk iclk~clkctrl F[2][4][9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.676 ns" { iclk iclk~combout iclk~clkctrl F[2][4][9] } { 0.000ns 0.000ns 0.118ns 1.022ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "19.128 ns" { d3[1] DCT_1d_8b:DCT_1d_8b|s3[1]~15 DCT_1d_8b:DCT_1d_8b|s3[2]~17 DCT_1d_8b:DCT_1d_8b|s3[3]~19 DCT_1d_8b:DCT_1d_8b|s3[4]~20 DCT_1d_8b:DCT_1d_8b|Add18~194 DCT_1d_8b:DCT_1d_8b|Add18~196 DCT_1d_8b:DCT_1d_8b|Add18~198 DCT_1d_8b:DCT_1d_8b|Add18~199 DCT_1d_8b:DCT_1d_8b|Add19~136 DCT_1d_8b:DCT_1d_8b|Add19~138 DCT_1d_8b:DCT_1d_8b|Add19~139 DCT_1d_8b:DCT_1d_8b|Add45~130 DCT_1d_8b:DCT_1d_8b|Add45~132 DCT_1d_8b:DCT_1d_8b|Add45~133 DCT_1d_8b:DCT_1d_8b|Add46~147 DCT_1d_8b:DCT_1d_8b|Add46~148 F[2][4][9]~feeder F[2][4][9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "19.128 ns" { d3[1] d3[1]~combout DCT_1d_8b:DCT_1d_8b|s3[1]~15 DCT_1d_8b:DCT_1d_8b|s3[2]~17 DCT_1d_8b:DCT_1d_8b|s3[3]~19 DCT_1d_8b:DCT_1d_8b|s3[4]~20 DCT_1d_8b:DCT_1d_8b|Add18~194 DCT_1d_8b:DCT_1d_8b|Add18~196 DCT_1d_8b:DCT_1d_8b|Add18~198 DCT_1d_8b:DCT_1d_8b|Add18~199 DCT_1d_8b:DCT_1d_8b|Add19~136 DCT_1d_8b:DCT_1d_8b|Add19~138 DCT_1d_8b:DCT_1d_8b|Add19~139 DCT_1d_8b:DCT_1d_8b|Add45~130 DCT_1d_8b:DCT_1d_8b|Add45~132 DCT_1d_8b:DCT_1d_8b|Add45~133 DCT_1d_8b:DCT_1d_8b|Add46~147 DCT_1d_8b:DCT_1d_8b|Add46~148 F[2][4][9]~feeder F[2][4][9] } { 0.000ns 0.000ns 5.776ns 0.000ns 0.000ns 0.000ns 2.814ns 0.000ns 0.000ns 0.000ns 1.264ns 0.000ns 0.000ns 0.693ns 0.000ns 0.000ns 1.153ns 0.000ns 1.784ns 0.000ns } { 0.000ns 0.840ns 0.414ns 0.071ns 0.071ns 0.410ns 0.393ns 0.159ns 0.071ns 0.410ns 0.393ns 0.071ns 0.410ns 0.414ns 0.071ns 0.410ns 0.393ns 0.410ns 0.149ns 0.084ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.676 ns" { iclk iclk~clkctrl F[2][4][9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.676 ns" { iclk iclk~combout iclk~clkctrl F[2][4][9] } { 0.000ns 0.000ns 0.118ns 1.022ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
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