📄 prev_cmp_dct.map.qmsg
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{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "ordered port 6 DCT_1d_13bS 8 17 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"DCT_1d_13bS\" is connected to a signal of width 8. The formal width of the signal in the module is 17. Extra bits will be left dangling without any fanout logic." { } { { "DCT.v" "DCT_1d_13bS" { Text "D:/verilog/dct/DCT/DCT.v" 34 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "ordered port 7 DCT_1d_13bS 8 17 " "Warning: Port \"ordered port 7\" on the entity instantiation of \"DCT_1d_13bS\" is connected to a signal of width 8. The formal width of the signal in the module is 17. Extra bits will be left dangling without any fanout logic." { } { { "DCT.v" "DCT_1d_13bS" { Text "D:/verilog/dct/DCT/DCT.v" 34 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[2\]\[0\]\[12\] data_in GND " "Warning: Reduced register \"F\[2\]\[0\]\[12\]\" with stuck data_in port to stuck value GND" { } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[2\]\[0\]\[11\] data_in GND " "Warning: Reduced register \"F\[2\]\[0\]\[11\]\" with stuck data_in port to stuck value GND" { } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[1\]\[0\]\[12\] data_in GND " "Warning: Reduced register \"F\[1\]\[0\]\[12\]\" with stuck data_in port to stuck value GND" { } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[1\]\[0\]\[11\] data_in GND " "Warning: Reduced register \"F\[1\]\[0\]\[11\]\" with stuck data_in port to stuck value GND" { } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[0\]\[0\]\[12\] data_in GND " "Warning: Reduced register \"F\[0\]\[0\]\[12\]\" with stuck data_in port to stuck value GND" { } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[0\]\[0\]\[11\] data_in GND " "Warning: Reduced register \"F\[0\]\[0\]\[11\]\" with stuck data_in port to stuck value GND" { } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[3\]\[0\]\[11\] data_in GND " "Warning: Reduced register \"F\[3\]\[0\]\[11\]\" with stuck data_in port to stuck value GND" { } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[4\]\[0\]\[11\] data_in GND " "Warning: Reduced register \"F\[4\]\[0\]\[11\]\" with stuck data_in port to stuck value GND" { } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[5\]\[0\]\[11\] data_in GND " "Warning: Reduced register \"F\[5\]\[0\]\[11\]\" with stuck data_in port to stuck value GND" { } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[5\]\[0\]\[12\] data_in GND " "Warning: Reduced register \"F\[5\]\[0\]\[12\]\" with stuck data_in port to stuck value GND" { } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[6\]\[0\]\[11\] data_in GND " "Warning: Reduced register \"F\[6\]\[0\]\[11\]\" with stuck data_in port to stuck value GND" { } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[6\]\[0\]\[12\] data_in GND " "Warning: Reduced register \"F\[6\]\[0\]\[12\]\" with stuck data_in port to stuck value GND" { } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[7\]\[0\]\[11\] data_in GND " "Warning: Reduced register \"F\[7\]\[0\]\[11\]\" with stuck data_in port to stuck value GND" { } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[7\]\[0\]\[12\] data_in GND " "Warning: Reduced register \"F\[7\]\[0\]\[12\]\" with stuck data_in port to stuck value GND" { } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "F0_S\[11\] GND " "Warning: Pin \"F0_S\[11\]\" stuck at GND" { } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 16 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "F0_S\[12\] GND " "Warning: Pin \"F0_S\[12\]\" stuck at GND" { } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 16 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} } { } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "66 66 " "Info: 66 registers lost all their fanouts during netlist optimizations. The first 66 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F4_r\[12\] " "Info: Register \"F4_r\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[4\]\[7\]\[12\] " "Info: Register \"F\[4\]\[7\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[4\]\[6\]\[12\] " "Info: Register \"F\[4\]\[6\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[4\]\[5\]\[12\] " "Info: Register \"F\[4\]\[5\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[4\]\[4\]\[12\] " "Info: Register \"F\[4\]\[4\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[4\]\[3\]\[12\] " "Info: Register \"F\[4\]\[3\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[4\]\[2\]\[12\] " "Info: Register \"F\[4\]\[2\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[4\]\[1\]\[12\] " "Info: Register \"F\[4\]\[1\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[4\]\[0\]\[12\] " "Info: Register \"F\[4\]\[0\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F3_r\[12\] " "Info: Register \"F3_r\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[3\]\[7\]\[12\] " "Info: Register \"F\[3\]\[7\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[3\]\[6\]\[12\] " "Info: Register \"F\[3\]\[6\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[3\]\[5\]\[12\] " "Info: Register \"F\[3\]\[5\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[3\]\[4\]\[12\] " "Info: Register \"F\[3\]\[4\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[3\]\[3\]\[12\] " "Info: Register \"F\[3\]\[3\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[3\]\[2\]\[12\] " "Info: Register \"F\[3\]\[2\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[3\]\[1\]\[12\] " "Info: Register \"F\[3\]\[1\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[3\]\[0\]\[12\] " "Info: Register \"F\[3\]\[0\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F5_r\[12\] " "Info: Register \"F5_r\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[5\]\[7\]\[12\] " "Info: Register \"F\[5\]\[7\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[5\]\[6\]\[12\] " "Info: Register \"F\[5\]\[6\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[5\]\[5\]\[12\] " "Info: Register \"F\[5\]\[5\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[5\]\[4\]\[12\] " "Info: Register \"F\[5\]\[4\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[5\]\[3\]\[12\] " "Info: Register \"F\[5\]\[3\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[5\]\[2\]\[12\] " "Info: Register \"F\[5\]\[2\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[5\]\[1\]\[12\] " "Info: Register \"F\[5\]\[1\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F2_r\[12\] " "Info: Register \"F2_r\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[2\]\[7\]\[12\] " "Info: Register \"F\[2\]\[7\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[2\]\[6\]\[12\] " "Info: Register \"F\[2\]\[6\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[2\]\[5\]\[12\] " "Info: Register \"F\[2\]\[5\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[2\]\[4\]\[12\] " "Info: Register \"F\[2\]\[4\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[2\]\[3\]\[12\] " "Info: Register \"F\[2\]\[3\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[2\]\[2\]\[12\] " "Info: Register \"F\[2\]\[2\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[2\]\[1\]\[12\] " "Info: Register \"F\[2\]\[1\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F7_r\[12\] " "Info: Register \"F7_r\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[7\]\[7\]\[12\] " "Info: Register \"F\[7\]\[7\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[7\]\[6\]\[12\] " "Info: Register \"F\[7\]\[6\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[7\]\[5\]\[12\] " "Info: Register \"F\[7\]\[5\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[7\]\[4\]\[12\] " "Info: Register \"F\[7\]\[4\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[7\]\[3\]\[12\] " "Info: Register \"F\[7\]\[3\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[7\]\[2\]\[12\] " "Info: Register \"F\[7\]\[2\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[7\]\[1\]\[12\] " "Info: Register \"F\[7\]\[1\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F6_r\[12\] " "Info: Register \"F6_r\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[6\]\[7\]\[12\] " "Info: Register \"F\[6\]\[7\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[6\]\[6\]\[12\] " "Info: Register \"F\[6\]\[6\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[6\]\[5\]\[12\] " "Info: Register \"F\[6\]\[5\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[6\]\[4\]\[12\] " "Info: Register \"F\[6\]\[4\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[6\]\[3\]\[12\] " "Info: Register \"F\[6\]\[3\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[6\]\[2\]\[12\] " "Info: Register \"F\[6\]\[2\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[6\]\[1\]\[12\] " "Info: Register \"F\[6\]\[1\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F1_r\[12\] " "Info: Register \"F1_r\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[1\]\[7\]\[12\] " "Info: Register \"F\[1\]\[7\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[1\]\[6\]\[12\] " "Info: Register \"F\[1\]\[6\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[1\]\[5\]\[12\] " "Info: Register \"F\[1\]\[5\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[1\]\[4\]\[12\] " "Info: Register \"F\[1\]\[4\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[1\]\[3\]\[12\] " "Info: Register \"F\[1\]\[3\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[1\]\[2\]\[12\] " "Info: Register \"F\[1\]\[2\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[1\]\[1\]\[12\] " "Info: Register \"F\[1\]\[1\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F0_r\[12\] " "Info: Register \"F0_r\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[0\]\[7\]\[12\] " "Info: Register \"F\[0\]\[7\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[0\]\[6\]\[12\] " "Info: Register \"F\[0\]\[6\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[0\]\[5\]\[12\] " "Info: Register \"F\[0\]\[5\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[0\]\[4\]\[12\] " "Info: Register \"F\[0\]\[4\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[0\]\[3\]\[12\] " "Info: Register \"F\[0\]\[3\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[0\]\[2\]\[12\] " "Info: Register \"F\[0\]\[2\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "F\[0\]\[1\]\[12\] " "Info: Register \"F\[0\]\[1\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} } { } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "2900 " "Info: Implemented 2900 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "66 " "Info: Implemented 66 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "177 " "Info: Implemented 177 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "2657 " "Info: Implemented 2657 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 77 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 77 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "146 " "Info: Allocated 146 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 12 16:37:46 2008 " "Info: Processing ended: Thu Jun 12 16:37:46 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
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