prev_cmp_dct.map.qmsg

8x8DCT verilog code 一次輸入8個點

{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "show2\[0\] DCT_1d_8b.v(19) " "Warning (10034): Output port \"show2\[0\]\" at DCT_1d_8b.v(19) has no driver" {  } { { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "show3\[9\] DCT_1d_8b.v(19) " "Warning (10034): Output port \"show3\[9\]\" at DCT_1d_8b.v(19) has no driver" {  } { { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "show3\[8\] DCT_1d_8b.v(19) " "Warning (10034): Output port \"show3\[8\]\" at DCT_1d_8b.v(19) has no driver" {  } { { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "show3\[7\] DCT_1d_8b.v(19) " "Warning (10034): Output port \"show3\[7\]\" at DCT_1d_8b.v(19) has no driver" {  } { { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "show3\[6\] DCT_1d_8b.v(19) " "Warning (10034): Output port \"show3\[6\]\" at DCT_1d_8b.v(19) has no driver" {  } { { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "show3\[5\] DCT_1d_8b.v(19) " "Warning (10034): Output port \"show3\[5\]\" at DCT_1d_8b.v(19) has no driver" {  } { { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "show3\[4\] DCT_1d_8b.v(19) " "Warning (10034): Output port \"show3\[4\]\" at DCT_1d_8b.v(19) has no driver" {  } { { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "show3\[3\] DCT_1d_8b.v(19) " "Warning (10034): Output port \"show3\[3\]\" at DCT_1d_8b.v(19) has no driver" {  } { { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "show3\[2\] DCT_1d_8b.v(19) " "Warning (10034): Output port \"show3\[2\]\" at DCT_1d_8b.v(19) has no driver" {  } { { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "show3\[1\] DCT_1d_8b.v(19) " "Warning (10034): Output port \"show3\[1\]\" at DCT_1d_8b.v(19) has no driver" {  } { { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "show3\[0\] DCT_1d_8b.v(19) " "Warning (10034): Output port \"show3\[0\]\" at DCT_1d_8b.v(19) has no driver" {  } { { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "B4DM.v 1 1 " "Warning: Using design file B4DM.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 B4DM " "Info: Found entity 1: B4DM" {  } { { "B4DM.v" "" { Text "D:/verilog/dct/DCT/B4DM.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "B4DM DCT_1d_8b:DCT_1d_8b\|B4DM:B4DM0 " "Info: Elaborating entity \"B4DM\" for hierarchy \"DCT_1d_8b:DCT_1d_8b\|B4DM:B4DM0\"" {  } { { "DCT_1d_8b.v" "B4DM0" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 62 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "DCT_1d_13bS.v 1 1 " "Warning: Using design file DCT_1d_13bS.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 DCT_1d_13bS " "Info: Found entity 1: DCT_1d_13bS" {  } { { "DCT_1d_13bS.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_13bS.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DCT_1d_13bS DCT_1d_13bS:DCT_1d_13bS " "Info: Elaborating entity \"DCT_1d_13bS\" for hierarchy \"DCT_1d_13bS:DCT_1d_13bS\"" {  } { { "DCT.v" "DCT_1d_13bS" { Text "D:/verilog/dct/DCT/DCT.v" 34 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "B4DM2.v 1 1 " "Warning: Using design file B4DM2.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 B4DM2 " "Info: Found entity 1: B4DM2" {  } { { "B4DM2.v" "" { Text "D:/verilog/dct/DCT/B4DM2.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "B4DM2 DCT_1d_13bS:DCT_1d_13bS\|B4DM2:B4DM20 " "Info: Elaborating entity \"B4DM2\" for hierarchy \"DCT_1d_13bS:DCT_1d_13bS\|B4DM2:B4DM20\"" {  } { { "DCT_1d_13bS.v" "B4DM20" { Text "D:/verilog/dct/DCT/DCT_1d_13bS.v" 53 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "ordered port 0 DCT_1d_13bS 8 17 " "Warning: Port \"ordered port 0\" on the entity instantiation of \"DCT_1d_13bS\" is connected to a signal of width 8. The formal width of the signal in the module is 17.  Extra bits will be left dangling without any fanout logic." {  } { { "DCT.v" "DCT_1d_13bS" { Text "D:/verilog/dct/DCT/DCT.v" 34 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "ordered port 1 DCT_1d_13bS 8 17 " "Warning: Port \"ordered port 1\" on the entity instantiation of \"DCT_1d_13bS\" is connected to a signal of width 8. The formal width of the signal in the module is 17.  Extra bits will be left dangling without any fanout logic." {  } { { "DCT.v" "DCT_1d_13bS" { Text "D:/verilog/dct/DCT/DCT.v" 34 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "ordered port 2 DCT_1d_13bS 8 17 " "Warning: Port \"ordered port 2\" on the entity instantiation of \"DCT_1d_13bS\" is connected to a signal of width 8. The formal width of the signal in the module is 17.  Extra bits will be left dangling without any fanout logic." {  } { { "DCT.v" "DCT_1d_13bS" { Text "D:/verilog/dct/DCT/DCT.v" 34 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "ordered port 3 DCT_1d_13bS 8 17 " "Warning: Port \"ordered port 3\" on the entity instantiation of \"DCT_1d_13bS\" is connected to a signal of width 8. The formal width of the signal in the module is 17.  Extra bits will be left dangling without any fanout logic." {  } { { "DCT.v" "DCT_1d_13bS" { Text "D:/verilog/dct/DCT/DCT.v" 34 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "ordered port 4 DCT_1d_13bS 8 17 " "Warning: Port \"ordered port 4\" on the entity instantiation of \"DCT_1d_13bS\" is connected to a signal of width 8. The formal width of the signal in the module is 17.  Extra bits will be left dangling without any fanout logic." {  } { { "DCT.v" "DCT_1d_13bS" { Text "D:/verilog/dct/DCT/DCT.v" 34 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "ordered port 5 DCT_1d_13bS 8 17 " "Warning: Port \"ordered port 5\" on the entity instantiation of \"DCT_1d_13bS\" is connected to a signal of width 8. The formal width of the signal in the module is 17.  Extra bits will be left dangling without any fanout logic." {  } { { "DCT.v" "DCT_1d_13bS" { Text "D:/verilog/dct/DCT/DCT.v" 34 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 0 0 "" 0}