📄 dct.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "iclk register c1\[1\]~reg0 register F6_r\[12\] 193.87 MHz 5.158 ns Internal " "Info: Clock \"iclk\" has Internal fmax of 193.87 MHz between source register \"c1\[1\]~reg0\" and destination register \"F6_r\[12\]\" (period= 5.158 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.941 ns + Longest register register " "Info: + Longest register to register delay is 4.941 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns c1\[1\]~reg0 1 REG LCFF_X35_Y17_N1 310 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X35_Y17_N1; Fanout = 310; REG Node = 'c1\[1\]~reg0'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { c1[1]~reg0 } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 54 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.387 ns) + CELL(0.420 ns) 1.807 ns F4_r\[11\]~140 2 COMB LCCOMB_X34_Y17_N8 24 " "Info: 2: + IC(1.387 ns) + CELL(0.420 ns) = 1.807 ns; Loc. = LCCOMB_X34_Y17_N8; Fanout = 24; COMB Node = 'F4_r\[11\]~140'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.807 ns" { c1[1]~reg0 F4_r[11]~140 } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.703 ns) + CELL(0.420 ns) 2.930 ns Mux78~56 3 COMB LCCOMB_X35_Y17_N8 1 " "Info: 3: + IC(0.703 ns) + CELL(0.420 ns) = 2.930 ns; Loc. = LCCOMB_X35_Y17_N8; Fanout = 1; COMB Node = 'Mux78~56'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.123 ns" { F4_r[11]~140 Mux78~56 } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.910 ns) + CELL(0.150 ns) 3.990 ns Mux78~57 4 COMB LCCOMB_X35_Y17_N4 1 " "Info: 4: + IC(0.910 ns) + CELL(0.150 ns) = 3.990 ns; Loc. = LCCOMB_X35_Y17_N4; Fanout = 1; COMB Node = 'Mux78~57'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.060 ns" { Mux78~56 Mux78~57 } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.717 ns) + CELL(0.150 ns) 4.857 ns Mux78~58 5 COMB LCCOMB_X35_Y16_N2 1 " "Info: 5: + IC(0.717 ns) + CELL(0.150 ns) = 4.857 ns; Loc. = LCCOMB_X35_Y16_N2; Fanout = 1; COMB Node = 'Mux78~58'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.867 ns" { Mux78~57 Mux78~58 } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 4.941 ns F6_r\[12\] 6 REG LCFF_X35_Y16_N3 6 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 4.941 ns; Loc. = LCFF_X35_Y16_N3; Fanout = 6; REG Node = 'F6_r\[12\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { Mux78~58 F6_r[12] } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.224 ns ( 24.77 % ) " "Info: Total cell delay = 1.224 ns ( 24.77 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.717 ns ( 75.23 % ) " "Info: Total interconnect delay = 3.717 ns ( 75.23 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.941 ns" { c1[1]~reg0 F4_r[11]~140 Mux78~56 Mux78~57 Mux78~58 F6_r[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.941 ns" { c1[1]~reg0 F4_r[11]~140 Mux78~56 Mux78~57 Mux78~58 F6_r[12] } { 0.000ns 1.387ns 0.703ns 0.910ns 0.717ns 0.000ns } { 0.000ns 0.420ns 0.420ns 0.150ns 0.150ns 0.084ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.003 ns - Smallest " "Info: - Smallest clock skew is -0.003 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iclk destination 2.665 ns + Shortest register " "Info: + Shortest clock path from clock \"iclk\" to destination register is 2.665 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns iclk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'iclk'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { iclk } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns iclk~clkctrl 2 COMB CLKCTRL_G3 921 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 921; COMB Node = 'iclk~clkctrl'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { iclk iclk~clkctrl } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.011 ns) + CELL(0.537 ns) 2.665 ns F6_r\[12\] 3 REG LCFF_X35_Y16_N3 6 " "Info: 3: + IC(1.011 ns) + CELL(0.537 ns) = 2.665 ns; Loc. = LCFF_X35_Y16_N3; Fanout = 6; REG Node = 'F6_r\[12\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.548 ns" { iclk~clkctrl F6_r[12] } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.64 % ) " "Info: Total cell delay = 1.536 ns ( 57.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.129 ns ( 42.36 % ) " "Info: Total interconnect delay = 1.129 ns ( 42.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.665 ns" { iclk iclk~clkctrl F6_r[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.665 ns" { iclk iclk~combout iclk~clkctrl F6_r[12] } { 0.000ns 0.000ns 0.118ns 1.011ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iclk source 2.668 ns - Longest register " "Info: - Longest clock path from clock \"iclk\" to source register is 2.668 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns iclk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'iclk'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { iclk } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns iclk~clkctrl 2 COMB CLKCTRL_G3 921 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 921; COMB Node = 'iclk~clkctrl'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { iclk iclk~clkctrl } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.537 ns) 2.668 ns c1\[1\]~reg0 3 REG LCFF_X35_Y17_N1 310 " "Info: 3: + IC(1.014 ns) + CELL(0.537 ns) = 2.668 ns; Loc. = LCFF_X35_Y17_N1; Fanout = 310; REG Node = 'c1\[1\]~reg0'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.551 ns" { iclk~clkctrl c1[1]~reg0 } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 54 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.57 % ) " "Info: Total cell delay = 1.536 ns ( 57.57 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.132 ns ( 42.43 % ) " "Info: Total interconnect delay = 1.132 ns ( 42.43 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.668 ns" { iclk iclk~clkctrl c1[1]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.668 ns" { iclk iclk~combout iclk~clkctrl c1[1]~reg0 } { 0.000ns 0.000ns 0.118ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.665 ns" { iclk iclk~clkctrl F6_r[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.665 ns" { iclk iclk~combout iclk~clkctrl F6_r[12] } { 0.000ns 0.000ns 0.118ns 1.011ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.668 ns" { iclk iclk~clkctrl c1[1]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.668 ns" { iclk iclk~combout iclk~clkctrl c1[1]~reg0 } { 0.000ns 0.000ns 0.118ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" { } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 54 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 54 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.941 ns" { c1[1]~reg0 F4_r[11]~140 Mux78~56 Mux78~57 Mux78~58 F6_r[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.941 ns" { c1[1]~reg0 F4_r[11]~140 Mux78~56 Mux78~57 Mux78~58 F6_r[12] } { 0.000ns 1.387ns 0.703ns 0.910ns 0.717ns 0.000ns } { 0.000ns 0.420ns 0.420ns 0.150ns 0.150ns 0.084ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.665 ns" { iclk iclk~clkctrl F6_r[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.665 ns" { iclk iclk~combout iclk~clkctrl F6_r[12] } { 0.000ns 0.000ns 0.118ns 1.011ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.668 ns" { iclk iclk~clkctrl c1[1]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.668 ns" { iclk iclk~combout iclk~clkctrl c1[1]~reg0 } { 0.000ns 0.000ns 0.118ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "F\[5\]\[6\]\[11\] d6\[0\] iclk 19.103 ns register " "Info: tsu for register \"F\[5\]\[6\]\[11\]\" (data pin = \"d6\[0\]\", clock pin = \"iclk\") is 19.103 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "21.803 ns + Longest pin register " "Info: + Longest pin to register delay is 21.803 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.830 ns) 0.830 ns d6\[0\] 1 PIN PIN_H11 2 " "Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_H11; Fanout = 2; PIN Node = 'd6\[0\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { d6[0] } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.309 ns) + CELL(0.414 ns) 7.553 ns DCT_1d_8b:DCT_1d_8b\|S1\[0\]~29 2 COMB LCCOMB_X29_Y24_N0 2 " "Info: 2: + IC(6.309 ns) + CELL(0.414 ns) = 7.553 ns; Loc. = LCCOMB_X29_Y24_N0; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|S1\[0\]~29'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.723 ns" { d6[0] DCT_1d_8b:DCT_1d_8b|S1[0]~29 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 7.624 ns DCT_1d_8b:DCT_1d_8b\|S1\[1\]~31 3 COMB LCCOMB_X29_Y24_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 7.624 ns; Loc. = LCCOMB_X29_Y24_N2; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|S1\[1\]~31'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DCT_1d_8b:DCT_1d_8b|S1[0]~29 DCT_1d_8b:DCT_1d_8b|S1[1]~31 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 7.695 ns DCT_1d_8b:DCT_1d_8b\|S1\[2\]~33 4 COMB LCCOMB_X29_Y24_N4 2 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 7.695 ns; Loc. = LCCOMB_X29_Y24_N4; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|S1\[2\]~33'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DCT_1d_8b:DCT_1d_8b|S1[1]~31 DCT_1d_8b:DCT_1d_8b|S1[2]~33 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 7.766 ns DCT_1d_8b:DCT_1d_8b\|S1\[3\]~35 5 COMB LCCOMB_X29_Y24_N6 2 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 7.766 ns; Loc. = LCCOMB_X29_Y24_N6; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|S1\[3\]~35'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DCT_1d_8b:DCT_1d_8b|S1[2]~33 DCT_1d_8b:DCT_1d_8b|S1[3]~35 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 8.176 ns DCT_1d_8b:DCT_1d_8b\|S1\[4\]~36 6 COMB LCCOMB_X29_Y24_N8 16 " "Info: 6: + IC(0.000 ns) + CELL(0.410 ns) = 8.176 ns; Loc. = LCCOMB_X29_Y24_N8; Fanout = 16; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|S1\[4\]~36'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { DCT_1d_8b:DCT_1d_8b|S1[3]~35 DCT_1d_8b:DCT_1d_8b|S1[4]~36 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.204 ns) + CELL(0.414 ns) 11.794 ns DCT_1d_8b:DCT_1d_8b\|B4DM:B4DM9\|Add0~140 7 COMB LCCOMB_X40_Y14_N12 2 " "Info: 7: + IC(3.204 ns) + CELL(0.414 ns) = 11.794 ns; Loc. = LCCOMB_X40_Y14_N12; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|B4DM:B4DM9\|Add0~140'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.618 ns" { DCT_1d_8b:DCT_1d_8b|S1[4]~36 DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9|Add0~140 } "NODE_NAME" } } { "B4DM.v" "" { Text "D:/verilog/dct/DCT/B4DM.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 12.204 ns DCT_1d_8b:DCT_1d_8b\|B4DM:B4DM9\|Add0~141 8 COMB LCCOMB_X40_Y14_N14 2 " "Info: 8: + IC(0.000 ns) + CELL(0.410 ns) = 12.204 ns; Loc. = LCCOMB_X40_Y14_N14; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|B4DM:B4DM9\|Add0~141'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9|Add0~140 DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9|Add0~141 } "NODE_NAME" } } { "B4DM.v" "" { Text "D:/verilog/dct/DCT/B4DM.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.412 ns) + CELL(0.414 ns) 13.030 ns DCT_1d_8b:DCT_1d_8b\|B4DM:B4DM9\|Add1~124 9 COMB LCCOMB_X41_Y14_N12 2 " "Info: 9: + IC(0.412 ns) + CELL(0.414 ns) = 13.030 ns; Loc. = LCCOMB_X41_Y14_N12; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|B4DM:B4DM9\|Add1~124'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.826 ns" { DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9|Add0~141 DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9|Add1~124 } "NODE_NAME" } } { "B4DM.v" "" { Text "D:/verilog/dct/DCT/B4DM.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 13.440 ns DCT_1d_8b:DCT_1d_8b\|B4DM:B4DM9\|Add1~125 10 COMB LCCOMB_X41_Y14_N14 2 " "Info: 10: + IC(0.000 ns) + CELL(0.410 ns) = 13.440 ns; Loc. = LCCOMB_X41_Y14_N14; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|B4DM:B4DM9\|Add1~125'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9|Add1~124 DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9|Add1~125 } "NODE_NAME" } } { "B4DM.v" "" { Text "D:/verilog/dct/DCT/B4DM.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.040 ns) + CELL(0.393 ns) 14.873 ns DCT_1d_8b:DCT_1d_8b\|Add17~165 11 COMB LCCOMB_X41_Y18_N8 2 " "Info: 11: + IC(1.040 ns) + CELL(0.393 ns) = 14.873 ns; Loc. = LCCOMB_X41_Y18_N8; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|Add17~165'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.433 ns" { DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9|Add1~125 DCT_1d_8b:DCT_1d_8b|Add17~165 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 15.283 ns DCT_1d_8b:DCT_1d_8b\|Add17~166 12 COMB LCCOMB_X41_Y18_N10 2 " "Info: 12: + IC(0.000 ns) + CELL(0.410 ns) = 15.283 ns; Loc. = LCCOMB_X41_Y18_N10; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|Add17~166'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { DCT_1d_8b:DCT_1d_8b|Add17~165 DCT_1d_8b:DCT_1d_8b|Add17~166 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.454 ns) + CELL(0.414 ns) 16.151 ns DCT_1d_8b:DCT_1d_8b\|Add18~167 13 COMB LCCOMB_X42_Y18_N12 2 " "Info: 13: + IC(0.454 ns) + CELL(0.414 ns) = 16.151 ns; Loc. = LCCOMB_X42_Y18_N12; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|Add18~167'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.868 ns" { DCT_1d_8b:DCT_1d_8b|Add17~166 DCT_1d_8b:DCT_1d_8b|Add18~167 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 16.310 ns DCT_1d_8b:DCT_1d_8b\|Add18~169 14 COMB LCCOMB_X42_Y18_N14 2 " "Info: 14: + IC(0.000 ns) + CELL(0.159 ns) = 16.310 ns; Loc. = LCCOMB_X42_Y18_N14; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|Add18~169'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.159 ns" { DCT_1d_8b:DCT_1d_8b|Add18~167 DCT_1d_8b:DCT_1d_8b|Add18~169 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 16.720 ns DCT_1d_8b:DCT_1d_8b\|Add18~170 15 COMB LCCOMB_X42_Y18_N16 2 " "Info: 15: + IC(0.000 ns) + CELL(0.410 ns) = 16.720 ns; Loc. = LCCOMB_X42_Y18_N16; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|Add18~170'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { DCT_1d_8b:DCT_1d_8b|Add18~169 DCT_1d_8b:DCT_1d_8b|Add18~170 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.486 ns) + CELL(0.414 ns) 18.620 ns DCT_1d_8b:DCT_1d_8b\|F6\[7\]~41 16 COMB LCCOMB_X35_Y18_N18 2 " "Info: 16: + IC(1.486 ns) + CELL(0.414 ns) = 18.620 ns; Loc. = LCCOMB_X35_Y18_N18; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|F6\[7\]~41'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { DCT_1d_8b:DCT_1d_8b|Add18~170 DCT_1d_8b:DCT_1d_8b|F6[7]~41 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 18.691 ns DCT_1d_8b:DCT_1d_8b\|F6\[8\]~43 17 COMB LCCOMB_X35_Y18_N20 2 " "Info: 17: + IC(0.000 ns) + CELL(0.071 ns) = 18.691 ns; Loc. = LCCOMB_X35_Y18_N20; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|F6\[8\]~43'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DCT_1d_8b:DCT_1d_8b|F6[7]~41 DCT_1d_8b:DCT_1d_8b|F6[8]~43 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 18.762 ns DCT_1d_8b:DCT_1d_8b\|F6\[9\]~45 18 COMB LCCOMB_X35_Y18_N22 2 " "Info: 18: + IC(0.000 ns) + CELL(0.071 ns) = 18.762 ns; Loc. = LCCOMB_X35_Y18_N22; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|F6\[9\]~45'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DCT_1d_8b:DCT_1d_8b|F6[8]~43 DCT_1d_8b:DCT_1d_8b|F6[9]~45 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 18.833 ns DCT_1d_8b:DCT_1d_8b\|F6\[10\]~47 19 COMB LCCOMB_X35_Y18_N24 2 " "Info: 19: + IC(0.000 ns) + CELL(0.071 ns) = 18.833 ns; Loc. = LCCOMB_X35_Y18_N24; Fanout = 2; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|F6\[10\]~47'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DCT_1d_8b:DCT_1d_8b|F6[9]~45 DCT_1d_8b:DCT_1d_8b|F6[10]~47 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 19.243 ns DCT_1d_8b:DCT_1d_8b\|F6\[11\]~48 20 COMB LCCOMB_X35_Y18_N26 9 " "Info: 20: + IC(0.000 ns) + CELL(0.410 ns) = 19.243 ns; Loc. = LCCOMB_X35_Y18_N26; Fanout = 9; COMB Node = 'DCT_1d_8b:DCT_1d_8b\|F6\[11\]~48'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { DCT_1d_8b:DCT_1d_8b|F6[10]~47 DCT_1d_8b:DCT_1d_8b|F6[11]~48 } "NODE_NAME" } } { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.194 ns) + CELL(0.366 ns) 21.803 ns F\[5\]\[6\]\[11\] 21 REG LCFF_X34_Y16_N9 1 " "Info: 21: + IC(2.194 ns) + CELL(0.366 ns) = 21.803 ns; Loc. = LCFF_X34_Y16_N9; Fanout = 1; REG Node = 'F\[5\]\[6\]\[11\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.560 ns" { DCT_1d_8b:DCT_1d_8b|F6[11]~48 F[5][6][11] } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.704 ns ( 30.75 % ) " "Info: Total cell delay = 6.704 ns ( 30.75 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.099 ns ( 69.25 % ) " "Info: Total interconnect delay = 15.099 ns ( 69.25 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "21.803 ns" { d6[0] DCT_1d_8b:DCT_1d_8b|S1[0]~29 DCT_1d_8b:DCT_1d_8b|S1[1]~31 DCT_1d_8b:DCT_1d_8b|S1[2]~33 DCT_1d_8b:DCT_1d_8b|S1[3]~35 DCT_1d_8b:DCT_1d_8b|S1[4]~36 DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9|Add0~140 DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9|Add0~141 DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9|Add1~124 DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9|Add1~125 DCT_1d_8b:DCT_1d_8b|Add17~165 DCT_1d_8b:DCT_1d_8b|Add17~166 DCT_1d_8b:DCT_1d_8b|Add18~167 DCT_1d_8b:DCT_1d_8b|Add18~169 DCT_1d_8b:DCT_1d_8b|Add18~170 DCT_1d_8b:DCT_1d_8b|F6[7]~41 DCT_1d_8b:DCT_1d_8b|F6[8]~43 DCT_1d_8b:DCT_1d_8b|F6[9]~45 DCT_1d_8b:DCT_1d_8b|F6[10]~47 DCT_1d_8b:DCT_1d_8b|F6[11]~48 F[5][6][11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "21.803 ns" { d6[0] d6[0]~combout DCT_1d_8b:DCT_1d_8b|S1[0]~29 DCT_1d_8b:DCT_1d_8b|S1[1]~31 DCT_1d_8b:DCT_1d_8b|S1[2]~33 DCT_1d_8b:DCT_1d_8b|S1[3]~35 DCT_1d_8b:DCT_1d_8b|S1[4]~36 DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9|Add0~140 DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9|Add0~141 DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9|Add1~124 DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9|Add1~125 DCT_1d_8b:DCT_1d_8b|Add17~165 DCT_1d_8b:DCT_1d_8b|Add17~166 DCT_1d_8b:DCT_1d_8b|Add18~167 DCT_1d_8b:DCT_1d_8b|Add18~169 DCT_1d_8b:DCT_1d_8b|Add18~170 DCT_1d_8b:DCT_1d_8b|F6[7]~41 DCT_1d_8b:DCT_1d_8b|F6[8]~43 DCT_1d_8b:DCT_1d_8b|F6[9]~45 DCT_1d_8b:DCT_1d_8b|F6[10]~47 DCT_1d_8b:DCT_1d_8b|F6[11]~48 F[5][6][11] } { 0.000ns 0.000ns 6.309ns 0.000ns 0.000ns 0.000ns 0.000ns 3.204ns 0.000ns 0.412ns 0.000ns 1.040ns 0.000ns 0.454ns 0.000ns 0.000ns 1.486ns 0.000ns 0.000ns 0.000ns 0.000ns 2.194ns } { 0.000ns 0.830ns 0.414ns 0.071ns 0.071ns 0.071ns 0.410ns 0.414ns 0.410ns 0.414ns 0.410ns 0.393ns 0.410ns 0.414ns 0.159ns 0.410ns 0.414ns 0.071ns 0.071ns 0.071ns 0.410ns 0.366ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iclk destination 2.664 ns - Shortest register " "Info: - Shortest clock path from clock \"iclk\" to destination register is 2.664 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns iclk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'iclk'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { iclk } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns iclk~clkctrl 2 COMB CLKCTRL_G3 921 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 921; COMB Node = 'iclk~clkctrl'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { iclk iclk~clkctrl } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.010 ns) + CELL(0.537 ns) 2.664 ns F\[5\]\[6\]\[11\] 3 REG LCFF_X34_Y16_N9 1 " "Info: 3: + IC(1.010 ns) + CELL(0.537 ns) = 2.664 ns; Loc. = LCFF_X34_Y16_N9; Fanout = 1; REG Node = 'F\[5\]\[6\]\[11\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.547 ns" { iclk~clkctrl F[5][6][11] } "NODE_NAME" } } { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.66 % ) " "Info: Total cell delay = 1.536 ns ( 57.66 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.128 ns ( 42.34 % ) " "Info: Total interconnect delay = 1.128 ns ( 42.34 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.664 ns" { iclk iclk~clkctrl F[5][6][11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.664 ns" { iclk iclk~combout iclk~clkctrl F[5][6][11] } { 0.000ns 0.000ns 0.118ns 1.010ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "21.803 ns" { d6[0] DCT_1d_8b:DCT_1d_8b|S1[0]~29 DCT_1d_8b:DCT_1d_8b|S1[1]~31 DCT_1d_8b:DCT_1d_8b|S1[2]~33 DCT_1d_8b:DCT_1d_8b|S1[3]~35 DCT_1d_8b:DCT_1d_8b|S1[4]~36 DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9|Add0~140 DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9|Add0~141 DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9|Add1~124 DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9|Add1~125 DCT_1d_8b:DCT_1d_8b|Add17~165 DCT_1d_8b:DCT_1d_8b|Add17~166 DCT_1d_8b:DCT_1d_8b|Add18~167 DCT_1d_8b:DCT_1d_8b|Add18~169 DCT_1d_8b:DCT_1d_8b|Add18~170 DCT_1d_8b:DCT_1d_8b|F6[7]~41 DCT_1d_8b:DCT_1d_8b|F6[8]~43 DCT_1d_8b:DCT_1d_8b|F6[9]~45 DCT_1d_8b:DCT_1d_8b|F6[10]~47 DCT_1d_8b:DCT_1d_8b|F6[11]~48 F[5][6][11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "21.803 ns" { d6[0] d6[0]~combout DCT_1d_8b:DCT_1d_8b|S1[0]~29 DCT_1d_8b:DCT_1d_8b|S1[1]~31 DCT_1d_8b:DCT_1d_8b|S1[2]~33 DCT_1d_8b:DCT_1d_8b|S1[3]~35 DCT_1d_8b:DCT_1d_8b|S1[4]~36 DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9|Add0~140 DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9|Add0~141 DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9|Add1~124 DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9|Add1~125 DCT_1d_8b:DCT_1d_8b|Add17~165 DCT_1d_8b:DCT_1d_8b|Add17~166 DCT_1d_8b:DCT_1d_8b|Add18~167 DCT_1d_8b:DCT_1d_8b|Add18~169 DCT_1d_8b:DCT_1d_8b|Add18~170 DCT_1d_8b:DCT_1d_8b|F6[7]~41 DCT_1d_8b:DCT_1d_8b|F6[8]~43 DCT_1d_8b:DCT_1d_8b|F6[9]~45 DCT_1d_8b:DCT_1d_8b|F6[10]~47 DCT_1d_8b:DCT_1d_8b|F6[11]~48 F[5][6][11] } { 0.000ns 0.000ns 6.309ns 0.000ns 0.000ns 0.000ns 0.000ns 3.204ns 0.000ns 0.412ns 0.000ns 1.040ns 0.000ns 0.454ns 0.000ns 0.000ns 1.486ns 0.000ns 0.000ns 0.000ns 0.000ns 2.194ns } { 0.000ns 0.830ns 0.414ns 0.071ns 0.071ns 0.071ns 0.410ns 0.414ns 0.410ns 0.414ns 0.410ns 0.393ns 0.410ns 0.414ns 0.159ns 0.410ns 0.414ns 0.071ns 0.071ns 0.071ns 0.410ns 0.366ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.664 ns" { iclk iclk~clkctrl F[5][6][11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.664 ns" { iclk iclk~combout iclk~clkctrl F[5][6][11] } { 0.000ns 0.000ns 0.118ns 1.010ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -