dct_1d_12b.v.bak

8x8DCT verilog code 一次輸入8個點

module DCT_1d_12b(
F0,F1,F2,F3,F4,F5,F6,F7,
d0,d1,d2,d3,d4,d5,d6,d7,
//iclk
//,address
);
//input iclk;
//input [2:0] address;

parameter n = 12;

input [n-1:0] d0,d1,d2,d3,d4,d5,d6,d7;

wire [n-1:0] d0,d1,d2,d3,d4,d5,d6,d7;

wire [n:0] s0,s1,s2,s3,s4,s5,s6,s7;
wire [3:0] a,b,c,d,e,f,g;
wire [3:0] a_i,b_i,c_i,d_i,e_i,f_i,g_i;
//reg [7:0] q;
//reg [2:0] address=3'b0;

//output q;
output [n+3:0] F0,F1,F2,F3,F4,F5,F6,F7;


assign a=4'b1011;
assign b=4'b1111;
assign c=4'b1110;
assign d=4'b1101;
assign e=4'b1000;
assign f=4'b0110;
assign g=4'b0011;

assign a_i=4'b0101;
assign b_i=4'b0001;
assign c_i=4'b0010;
assign d_i=4'b0011;
assign e_i=4'b1000;
assign f_i=4'b1010;
assign g_i=4'b1101;


//ROM u1 (.clock(iclk),.address(address),.q(q));

//assign d0	=	(address[2:0]==3'b000)?q:d0;
//assign d1	=	(address[2:0]==3'b001)?q:d1;
//assign d2	=	(address[2:0]==3'b010)?q:d2;
//assign d3	=	(address[2:0]==3'b011)?q:d3;
//assign d4	=	(address[2:0]==3'b100)?q:d4;
//assign d5	=	(address[2:0]==3'b101)?q:d5;
//assign d6	=	(address[2:0]==3'b110)?q:d6;
//assign d7	=	(address[2:0]==3'b111)?q:d7;

assign s0	=	d0+d7;
assign s1	=	d1+d6;
assign s2	=	d2+d5;
assign s3	=	d3+d4;
assign s4	=	d0-d7;
assign s5	=	d1-d6;
assign s6	=	d2-d5;
assign s7	=	d3-d4;

//a a  a  a s0 F0
//c f -f -c s1 F2
//a -a -a a s2 F4
//f -c c -f s3 F6 
//axs0
wire [n:0] axs0_r1,axs0_r2,axs0_r3,axs0_r4;
wire [n+3:0] axs0;
assign axs0_r1	=	(a[3]==0)?0:{1'b0,s0[8:1]};
assign axs0_r2	=	(a[2]==0)?0:{2'b00,s0[8:2]};
assign axs0_r3	=	(a[1]==0)?0:{3'b000,s0[8:3]};
assign axs0_r4	=	(a[0]==0)?0:{4'b0000,s0[8:4]};
assign axs0	=	(axs0_r1+axs0_r2+axs0_r3+axs0_r4) ;
//axs1
wire [n:0] axs1_r1,axs1_r2,axs1_r3,axs1_r4;
wire [n+3:0] axs1;
assign axs1_r1	=	(a[3]==0)?0:{1'b0,s1[8:1]};
assign axs1_r2	=	(a[2]==0)?0:{2'b00,s1[8:2]};
assign axs1_r3	=	(a[1]==0)?0:{3'b000,s1[8:3]};
assign axs1_r4	=	(a[0]==0)?0:{4'b0000,s1[8:4]};
assign axs1	=	(axs1_r1+axs1_r2+axs1_r3+axs1_r4) ;
//axs2
wire [n:0] axs2_r1,axs2_r2,axs2_r3,axs2_r4;
wire [n+3:0] axs2;
assign axs2_r1	=	(a[3]==0)?0:{1'b0,s2[8:1]};
assign axs2_r2	=	(a[2]==0)?0:{2'b00,s2[8:2]};
assign axs2_r3	=	(a[1]==0)?0:{3'b000,s2[8:3]};
assign axs2_r4	=	(a[0]==0)?0:{4'b0000,s2[8:4]};
assign axs2	=	(axs2_r1+axs2_r2+axs2_r3+axs2_r4) ;
//axs3
wire [n:0] axs3_r1,axs3_r2,axs3_r3,axs3_r4;
wire [n+3:0] axs3;
assign axs3_r1	=	(a[3]==0)?0:{1'b0,s3[8:1]};
assign axs3_r2	=	(a[2]==0)?0:{2'b00,s3[8:2]};
assign axs3_r3	=	(a[1]==0)?0:{3'b000,s3[8:3]};
assign axs3_r4	=	(a[0]==0)?0:{4'b0000,s3[8:4]};
assign axs3	=	(axs3_r1+axs3_r2+axs3_r3+axs3_r4) ;
//a a  a  a s0 F0
//			s1
//			s2
//			s3	
assign F0 = axs0+axs1+axs2+axs3;
//cxs0
wire [n:0] cxs0_r1,cxs0_r2,cxs0_r3,cxs0_r4;
wire [n+3:0] cxs0;
assign cxs0_r1	=	(c[3]==0)?0:{1'b0,s0[8:1]};
assign cxs0_r2	=	(c[2]==0)?0:{2'b00,s0[8:2]};
assign cxs0_r3	=	(c[1]==0)?0:{3'b000,s0[8:3]};
assign cxs0_r4	=	(c[0]==0)?0:{4'b0000,s0[8:4]};
assign cxs0	=	(cxs0_r1+cxs0_r2+cxs0_r3+cxs0_r4) ;
//fxs1
wire [n:0] fxs1_r1,fxs1_r2,fxs1_r3,fxs1_r4;
wire [n+3:0] fxs1;
assign fxs1_r1	=	(f[3]==0)?0:{1'b0,s1[8:1]};
assign fxs1_r2	=	(f[2]==0)?0:{2'b00,s1[8:2]};
assign fxs1_r3	=	(f[1]==0)?0:{3'b000,s1[8:3]};
assign fxs1_r4	=	(f[0]==0)?0:{4'b0000,s1[8:4]};
assign fxs1	=	(fxs1_r1+fxs1_r2+fxs1_r3+fxs1_r4) ;
//f_ixs2
wire [n:0] f_ixs2_r1,f_ixs2_r2,f_ixs2_r3,f_ixs2_r4;
wire [n+3:0] f_ixs2;
assign f_ixs2_r1	=	(f_i[3]==0)?0:{1'b0,s2[8:1]};
assign f_ixs2_r2	=	(f_i[2]==0)?0:{2'b00,s2[8:2]};
assign f_ixs2_r3	=	(f_i[1]==0)?0:{3'b000,s2[8:3]};
assign f_ixs2_r4	=	(f_i[0]==0)?0:{4'b0000,s2[8:4]};
assign f_ixs2	=	(f_ixs2_r1+f_ixs2_r2+f_ixs2_r3+f_ixs2_r4) ;
//c_ixs3
wire [n:0] c_ixs3_r1,c_ixs3_r2,c_ixs3_r3,c_ixs3_r4;
wire [n+3:0] c_ixs3;
assign c_ixs3_r1	=	(c_i[3]==0)?0:{1'b0,s3[8:1]};
assign c_ixs3_r2	=	(c_i[2]==0)?0:{2'b00,s3[8:2]};
assign c_ixs3_r3	=	(c_i[1]==0)?0:{3'b000,s3[8:3]};
assign c_ixs3_r4	=	(c_i[0]==0)?0:{4'b0000,s3[8:4]};
assign c_ixs3	=	(c_ixs3_r1+c_ixs3_r2+c_ixs3_r3+c_ixs3_r4) ;
//             s0 
///c f  -f  -c s1 F2
//			   s2
//			   s3
assign F2 = cxs0+fxs1+f_ixs2+c_ixs3;
//a_ixs1
wire [n:0] a_ixs1_r1,a_ixs1_r2,a_ixs1_r3,a_ixs1_r4;
wire [n+3:0] a_ixs1;
assign a_ixs1_r1	=	(a_i[3]==0)?0:{1'b0,s1[8:1]};
assign a_ixs1_r2	=	(a_i[2]==0)?0:{2'b00,s1[8:2]};
assign a_ixs1_r3	=	(a_i[1]==0)?0:{3'b000,s1[8:3]};
assign a_ixs1_r4	=	(a_i[0]==0)?0:{4'b0000,s1[8:4]};
assign a_ixs1	=	(a_ixs1_r1+a_ixs1_r2+a_ixs1_r3+a_ixs1_r4) ;
//a_ixs2
wire [n:0] a_ixs2_r1,a_ixs2_r2,a_ixs2_r3,a_ixs2_r4;
wire [n+3:0] a_ixs2;
assign a_ixs2_r1	=	(a_i[3]==0)?0:{1'b0,s2[8:1]};
assign a_ixs2_r2	=	(a_i[2]==0)?0:{2'b00,s2[8:2]};
assign a_ixs2_r3	=	(a_i[1]==0)?0:{3'b000,s2[8:3]};
assign a_ixs2_r4	=	(a_i[0]==0)?0:{4'b0000,s2[8:4]};
assign a_ixs2	=	(a_ixs2_r1+a_ixs2_r2+a_ixs2_r3+a_ixs2_r4) ;
//             s0 
//			   s1
///a -a -a  a  s2 F4
//			   s3
assign F4	=	axs0+a_ixs1+a_ixs2+axs3;
//fxs0
wire [n:0] fxs0_r1,fxs0_r2,fxs0_r3,fxs0_r4;
wire [n+3:0] fxs0;
assign fxs0_r1	=	(f[3]==0)?0:{1'b0,s0[8:1]};
assign fxs0_r2	=	(f[2]==0)?0:{2'b00,s0[8:2]};
assign fxs0_r3	=	(f[1]==0)?0:{3'b000,s0[8:3]};
assign fxs0_r4	=	(f[0]==0)?0:{4'b0000,s0[8:4]};
assign fxs0	=	(fxs0_r1+fxs0_r2+fxs0_r3+fxs0_r4) ;
//c_ixs1
wire [n:0] c_ixs1_r1,c_ixs1_r2,c_ixs1_r3,c_ixs1_r4;
wire [n+3:0] c_ixs1;
assign c_ixs1_r1	=	(c_i[3]==0)?0:{1'b0,s1[8:1]};
assign c_ixs1_r2	=	(c_i[2]==0)?0:{2'b00,s1[8:2]};
assign c_ixs1_r3	=	(c_i[1]==0)?0:{3'b000,s1[8:3]};
assign c_ixs1_r4	=	(c_i[0]==0)?0:{4'b0000,s1[8:4]};
assign c_ixs1	=	(c_ixs1_r1+c_ixs1_r2+c_ixs1_r3+c_ixs1_r4) ;
//cxs2
wire [n:0] cxs2_r1,cxs2_r2,cxs2_r3,cxs2_r4;
wire [n+3:0] cxs2;
assign cxs2_r1	=	(c[3]==0)?0:{1'b0,s2[8:1]};
assign cxs2_r2	=	(c[2]==0)?0:{2'b00,s2[8:2]};
assign cxs2_r3	=	(c[1]==0)?0:{3'b000,s2[8:3]};
assign cxs2_r4	=	(c[0]==0)?0:{4'b0000,s2[8:4]};
assign cxs2	=	(cxs2_r1+cxs2_r2+cxs2_r3+cxs2_r4) ;
//f_ixs3
wire [n:0] f_ixs3_r1,f_ixs3_r2,f_ixs3_r3,f_ixs3_r4;
wire [n+3:0] f_ixs3;
assign f_ixs3_r1	=	(f_i[3]==0)?0:{1'b0,s3[8:1]};
assign f_ixs3_r2	=	(f_i[2]==0)?0:{2'b00,s3[8:2]};
assign f_ixs3_r3	=	(f_i[1]==0)?0:{3'b000,s3[8:3]};
assign f_ixs3_r4	=	(f_i[0]==0)?0:{4'b0000,s3[8:4]};
assign f_ixs3	=	(f_ixs3_r1+f_ixs3_r2+f_ixs3_r3+f_ixs3_r4) ;
//           s0
//			 s1 
//			 s2
///f -c c -f s3 F6
assign F6	=	fxs0+c_ixs1+cxs2+f_ixs3;
//bxs4
wire [n:0] bxs4_r1,bxs4_r2,bxs4_r3,bxs4_r4;
wire [n+3:0] bxs4;
assign bxs4_r1	=	(b[3]==0)?0:{1'b0,s4[8:1]};
assign bxs4_r2	=	(b[2]==0)?0:{2'b00,s4[8:2]};
assign bxs4_r3	=	(b[1]==0)?0:{3'b000,s4[8:3]};
assign bxs4_r4	=	(b[0]==0)?0:{4'b0000,s4[8:4]};
assign bxs4	=	(bxs4_r1+bxs4_r2+bxs4_r3+bxs4_r4) ;
//dxs5
wire [n:0] dxs5_r1,dxs5_r2,dxs5_r3,dxs5_r4;
wire [n+3:0] dxs5;
assign dxs5_r1	=	(d[3]==0)?0:{1'b0,s5[8:1]};
assign dxs5_r2	=	(d[2]==0)?0:{2'b00,s5[8:2]};
assign dxs5_r3	=	(d[1]==0)?0:{3'b000,s5[8:3]};
assign dxs5_r4	=	(d[0]==0)?0:{4'b0000,s5[8:4]};
assign dxs5	=	(dxs5_r1+dxs5_r2+dxs5_r3+dxs5_r4) ;
//exs6
wire [n:0] exs6_r1,exs6_r2,exs6_r3,exs6_r4;
wire [n+3:0] exs6;
assign exs6_r1	=	(e[3]==0)?0:{1'b0,s6[8:1]};
assign exs6_r2	=	(e[2]==0)?0:{2'b00,s6[8:2]};
assign exs6_r3	=	(e[1]==0)?0:{3'b000,s6[8:3]};
assign exs6_r4	=	(e[0]==0)?0:{4'b0000,s6[8:4]};
assign exs6	=	(exs6_r1+exs6_r2+exs6_r3+exs6_r4) ;
//gxs7
wire [n:0] gxs7_r1,gxs7_r2,gxs7_r3,gxs7_r4;
wire [n+3:0] gxs7;
assign gxs7_r1	=	(g[3]==0)?0:{1'b0,s7[8:1]};
assign gxs7_r2	=	(g[2]==0)?0:{2'b00,s7[8:2]};
assign gxs7_r3	=	(g[1]==0)?0:{3'b000,s7[8:3]};
assign gxs7_r4	=	(g[0]==0)?0:{4'b0000,s7[8:4]};
assign gxs7	=	(gxs7_r1+gxs7_r2+gxs7_r3+gxs7_r4) ;
//b d e g s4 F1
//		  s5	 
//		  s6
//        s7
assign F1	=	bxs4+dxs5+exs6+gxs7;
//dxs4
wire [n:0] dxs4_r1,dxs4_r2,dxs4_r3,dxs4_r4;
wire [n+3:0] dxs4;
assign dxs4_r1	=	(d[3]==0)?0:{1'b0,s4[8:1]};
assign dxs4_r2	=	(d[2]==0)?0:{2'b00,s4[8:2]};
assign dxs4_r3	=	(d[1]==0)?0:{3'b000,s4[8:3]};
assign dxs4_r4	=	(d[0]==0)?0:{4'b0000,s4[8:4]};
assign dxs4	=	(dxs4_r1+dxs4_r2+dxs4_r3+dxs4_r4) ;
//g_ixs5
wire [n:0] g_ixs5_r1,g_ixs5_r2,g_ixs5_r3,g_ixs5_r4;
wire [n+3:0] g_ixs5;
assign g_ixs5_r1	=	(g_i[3]==0)?0:{1'b0,s5[8:1]};
assign g_ixs5_r2	=	(g_i[2]==0)?0:{2'b00,s5[8:2]};
assign g_ixs5_r3	=	(g_i[1]==0)?0:{3'b000,s5[8:3]};
assign g_ixs5_r4	=	(g_i[0]==0)?0:{4'b0000,s5[8:4]};
assign g_ixs5	=	(g_ixs5_r1+g_ixs5_r2+g_ixs5_r3+g_ixs5_r4) ;
//b_ixs6
wire [n:0] b_ixs6_r1,b_ixs6_r2,b_ixs6_r3,b_ixs6_r4;
wire [n+3:0] b_ixs6;
assign b_ixs6_r1	=	(b_i[3]==0)?0:{1'b0,s6[8:1]};
assign b_ixs6_r2	=	(b_i[2]==0)?0:{2'b00,s6[8:2]};
assign b_ixs6_r3	=	(b_i[1]==0)?0:{3'b000,s6[8:3]};
assign b_ixs6_r4	=	(b_i[0]==0)?0:{4'b0000,s6[8:4]};
assign b_ixs6	=	(b_ixs6_r1+b_ixs6_r2+b_ixs6_r3+b_ixs6_r4) ;
//e_ixs7
wire [n:0] e_ixs7_r1,e_ixs7_r2,e_ixs7_r3,e_ixs7_r4;
wire [n+3:0] e_ixs7;
assign e_ixs7_r1	=	(e_i[3]==0)?0:{1'b0,s7[8:1]};
assign e_ixs7_r2	=	(e_i[2]==0)?0:{2'b00,s7[8:2]};
assign e_ixs7_r3	=	(e_i[1]==0)?0:{3'b000,s7[8:3]};
assign e_ixs7_r4	=	(e_i[0]==0)?0:{4'b0000,s7[8:4]};
assign e_ixs7	=	(e_ixs7_r1+e_ixs7_r2+e_ixs7_r3+e_ixs7_r4) ;
//           s4
//d -g -b -e s5 F3	
//			 s6
//			 s7
assign F3	=	dxs4+g_ixs5+b_ixs6+e_ixs7;
//exs4
wire [n:0] exs4_r1,exs4_r2,exs4_r3,exs4_r4;
wire [n+3:0] exs4;
assign exs4_r1	=	(e[3]==0)?0:{1'b0,s4[8:1]};
assign exs4_r2	=	(e[2]==0)?0:{2'b00,s4[8:2]};
assign exs4_r3	=	(e[1]==0)?0:{3'b000,s4[8:3]};
assign exs4_r4	=	(e[0]==0)?0:{4'b0000,s4[8:4]};
assign exs4	=	(exs4_r1+exs4_r2+exs4_r3+exs4_r4) ;
//b_ixs5
wire [n:0] b_ixs5_r1,b_ixs5_r2,b_ixs5_r3,b_ixs5_r4;
wire [n+3:0] b_ixs5;
assign b_ixs5_r1	=	(b_i[3]==0)?0:{1'b0,s5[8:1]};
assign b_ixs5_r2	=	(b_i[2]==0)?0:{2'b00,s5[8:2]};
assign b_ixs5_r3	=	(b_i[1]==0)?0:{3'b000,s5[8:3]};
assign b_ixs5_r4	=	(b_i[0]==0)?0:{4'b0000,s5[8:4]};
assign b_ixs5	=	(b_ixs5_r1+b_ixs5_r2+b_ixs5_r3+b_ixs5_r4) ;
//gxs6
wire [n:0] gxs6_r1,gxs6_r2,gxs6_r3,gxs6_r4;
wire [n+3:0] gxs6;
assign gxs6_r1	=	(g[3]==0)?0:{1'b0,s6[8:1]};
assign gxs6_r2	=	(g[2]==0)?0:{2'b00,s6[8:2]};
assign gxs6_r3	=	(g[1]==0)?0:{3'b000,s6[8:3]};
assign gxs6_r4	=	(g[0]==0)?0:{4'b0000,s6[8:4]};
assign gxs6	=	(gxs6_r1+gxs6_r2+gxs6_r3+gxs6_r4) ;
//dxs7
wire [n:0] dxs7_r1,dxs7_r2,dxs7_r3,dxs7_r4;
wire [n+3:0] dxs7;
assign dxs7_r1	=	(d[3]==0)?0:{1'b0,s7[8:1]};
assign dxs7_r2	=	(d[2]==0)?0:{2'b00,s7[8:2]};
assign dxs7_r3	=	(d[1]==0)?0:{3'b000,s7[8:3]};
assign dxs7_r4	=	(d[0]==0)?0:{4'b0000,s7[8:4]};
assign dxs7	=	(dxs7_r1+dxs7_r2+dxs7_r3+dxs7_r4) ;
//           s4
//           s5	
//e -b g d   s6 F5
//			 s7
assign F5	=	exs4+b_ixs5+gxs6+dxs7;
//gxs4
wire [n:0] gxs4_r1,gxs4_r2,gxs4_r3,gxs4_r4;
wire [n+3:0] gxs4;
assign gxs4_r1	=	(g[3]==0)?0:{1'b0,s4[8:1]};
assign gxs4_r2	=	(g[2]==0)?0:{2'b00,s4[8:2]};
assign gxs4_r3	=	(g[1]==0)?0:{3'b000,s4[8:3]};
assign gxs4_r4	=	(g[0]==0)?0:{4'b0000,s4[8:4]};
assign gxs4	=	(gxs4_r1+gxs4_r2+gxs4_r3+gxs4_r4) ;
//e_ixs5
wire [n:0] e_ixs5_r1,e_ixs5_r2,e_ixs5_r3,e_ixs5_r4;
wire [n+3:0] e_ixs5;
assign e_ixs5_r1	=	(e_i[3]==0)?0:{1'b0,s5[8:1]};
assign e_ixs5_r2	=	(e_i[2]==0)?0:{2'b00,s5[8:2]};
assign e_ixs5_r3	=	(e_i[1]==0)?0:{3'b000,s5[8:3]};
assign e_ixs5_r4	=	(e_i[0]==0)?0:{4'b0000,s5[8:4]};
assign e_ixs5	=	(e_ixs5_r1+e_ixs5_r2+e_ixs5_r3+e_ixs5_r4) ;
//dxs6
wire [n:0] dxs6_r1,dxs6_r2,dxs6_r3,dxs6_r4;
wire [n+3:0] dxs6;
assign dxs6_r1	=	(d[3]==0)?0:{1'b0,s6[8:1]};
assign dxs6_r2	=	(d[2]==0)?0:{2'b00,s6[8:2]};
assign dxs6_r3	=	(d[1]==0)?0:{3'b000,s6[8:3]};
assign dxs6_r4	=	(d[0]==0)?0:{4'b0000,s6[8:4]};
assign dxs6	=	(dxs6_r1+dxs6_r2+dxs6_r3+dxs6_r4) ;
//b_ixs7
wire [n:0] b_ixs7_r1,b_ixs7_r2,b_ixs7_r3,b_ixs7_r4;
wire [n+3:0] b_ixs7;
assign b_ixs7_r1	=	(b_i[3]==0)?0:{1'b0,s7[8:1]};
assign b_ixs7_r2	=	(b_i[2]==0)?0:{2'b00,s7[8:2]};
assign b_ixs7_r3	=	(b_i[1]==0)?0:{3'b000,s7[8:3]};
assign b_ixs7_r4	=	(b_i[0]==0)?0:{4'b0000,s7[8:4]};
assign b_ixs7	=	(b_ixs7_r1+b_ixs7_r2+b_ixs7_r3+b_ixs7_r4) ;
//          s4
//			s5
//			s6
//g -e d -b s7 F7
assign F7	=	gxs4+e_ixs5+dxs6+b_ixs7;

//always @ (posedge iclk)
//begin
//	address = address+1;
//end
endmodule