dct.map.rpt

8x8DCT verilog code 一次輸入8個點

Analysis & Synthesis report for DCT
Thu Jun 12 16:42:49 2008
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Registers Removed During Synthesis
  8. General Register Statistics
  9. Multiplexer Restructuring Statistics (Restructuring Performed)
 10. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b
 11. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM0
 12. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM1
 13. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM2
 14. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM3
 15. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM4
 16. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM5
 17. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM6
 18. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM7
 19. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM8
 20. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM9
 21. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM10
 22. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM11
 23. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM12
 24. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM13
 25. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM14
 26. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM15
 27. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM16
 28. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM17
 29. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM18
 30. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM19
 31. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM20
 32. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM21
 33. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM22
 34. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM23
 35. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM24
 36. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM25
 37. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM26
 38. Parameter Settings for User Entity Instance: DCT_1d_8b:DCT_1d_8b|B4DM:B4DM27
 39. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS
 40. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM20
 41. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM21
 42. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM22
 43. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM23
 44. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM24
 45. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM25
 46. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM26
 47. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM27
 48. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM28
 49. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM29
 50. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM210
 51. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM211
 52. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM212
 53. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM213
 54. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM214
 55. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM215
 56. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM216
 57. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM217
 58. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM218
 59. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM219
 60. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM220
 61. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM221
 62. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM222
 63. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM223
 64. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM224
 65. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM225
 66. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM226
 67. Parameter Settings for User Entity Instance: DCT_1d_13bS:DCT_1d_13bS|B4DM2:B4DM227
 68. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Thu Jun 12 16:42:49 2008    ;
; Quartus II Version                 ; 7.1 Build 156 04/30/2007 SJ Full Version ;
; Revision Name                      ; DCT                                      ;
; Top-level Entity Name              ; DCT                                      ;
; Family                             ; Cyclone II                               ;
; Total logic elements               ; 2,389                                    ;
;     Total combinational functions  ; 2,389                                    ;
;     Dedicated logic registers      ; 921                                      ;
; Total registers                    ; 921                                      ;
; Total pins                         ; 315                                      ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 0                                        ;
; Embedded Multiplier 9-bit elements ; 0                                        ;
; Total PLLs                         ; 0                                        ;
+------------------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                            ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                         ; Setting            ; Default Value      ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                         ; EP2C35F672C6       ;                    ;
; Top-level entity name                                                          ; DCT                ; DCT                ;
; Family name                                                                    ; Cyclone II         ; Stratix II         ;
; Restructure Multiplexers                                                       ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                            ; Off                ; Off                ;
; Preserve fewer node names                                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                      ; Off                ; Off                ;
; Verilog Version                                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                                       ; Auto               ; Auto               ;
; Safe State Machine                                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                                              ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                                        ; On                 ; On                 ;
; DSP Block Balancing                                                            ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                             ; On                 ; On                 ;
; Power-Up Don't Care                                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                   ; Off                ; Off                ;
; Remove Duplicate Registers                                                     ; On                 ; On                 ;
; Ignore CARRY Buffers                                                           ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                          ; Off                ; Off                ;