dct_1d_13bs.v

8x8DCT verilog code 一次輸入8個點

module DCT_1d_13bS(
		F0,F1,F2,F3,F4,F5,F6,F7,
		d0,d1,d2,d3,d4,d5,d6,d7,
		S0,S1,S2,S3,S4,S5,S6,S7,
		show0,show1,show2,show3
		);

	parameter n = 13;

	input [n-1:0] d0,d1,d2,d3,d4,d5,d6,d7;

	wire [n-1:0] d0,d1,d2,d3,d4,d5,d6,d7;
	wire [3:0] a,b,c,d,e,f,g;

	output [n+3:0] F0,F1,F2,F3,F4,F5,F6,F7;
	output [n:0] S0,S1,S2,S3,S4,S5,S6,S7;
//	output [n-1:0] S0,S1,S2,S3,S4,S5,S6,S7;
	
	output [n:0] show0,show1,show2,show3;

	assign a=4'b1011;
	assign b=4'b1111;
	assign c=4'b1110;
	assign d=4'b1101;
	assign e=4'b1000;
	assign f=4'b0110;
	assign g=4'b0011;

	assign S0	=	{d0[n-1],d0} + {d7[n-1],d7};
	assign S1	=	{d1[n-1],d1} + {d6[n-1],d6};
	assign S2	=	{d2[n-1],d2} + {d5[n-1],d5};
	assign S3	=	{d3[n-1],d3} + {d4[n-1],d4};
	assign S4	=	{d0[n-1],d0} - {d7[n-1],d7};
	assign S5	=	{d1[n-1],d1} - {d6[n-1],d6};
	assign S6	=	{d2[n-1],d2} - {d5[n-1],d5};
	assign S7	=	{d3[n-1],d3} - {d4[n-1],d4};
	
	// ------------
	assign show0 = axs0_r;
	assign show1 = axs1_r;
	assign show2 = axs2_r;
	assign show3 = axs3_r;
	//-------------

//a a  a  a s0 F0
//c f -f -c s1 F2
//a -a -a a s2 F4
//f -c c -f s3 F6

// ------------------------- * F0 *
	wire [n:0]axs0_r,axs1_r,axs2_r,axs3_r;

	B4DM2 B4DM20(.A(S0),.B(a),.S(axs0_r));
	B4DM2 B4DM21(.A(S1),.B(a),.S(axs1_r));
	B4DM2 B4DM22(.A(S2),.B(a),.S(axs2_r));
	B4DM2 B4DM23(.A(S3),.B(a),.S(axs3_r));
	
	assign F0 = {{3{axs0_r[n]}}, axs0_r} + {{3{axs1_r[n]}}, axs1_r} + {{3{axs2_r[n]}}, axs2_r} + {{3{axs3_r[n]}}, axs3_r};

// ------------------------- * F2 *
	wire [n:0]cxs0_r,fxs1_r,fxs2_r,cxs3_r;

	B4DM2 B4DM24(.A(S0),.B(c),.S(cxs0_r));
	B4DM2 B4DM25(.A(S1),.B(f),.S(fxs1_r));
	B4DM2 B4DM26(.A(S2),.B(f),.S(fxs2_r));
	B4DM2 B4DM27(.A(S3),.B(c),.S(cxs3_r));

	assign F2 = {{3{cxs0_r[n]}}, cxs0_r} + {{3{fxs1_r[n]}}, fxs1_r} - {{3{fxs2_r[n]}}, fxs2_r} - {{3{cxs3_r[n]}}, cxs3_r};

// ------------------------- * F4 *

	assign F4 = {{3{axs0_r[n]}}, axs0_r} - {{3{axs1_r[n]}}, axs1_r} - {{3{axs2_r[n]}}, axs2_r} + {{3{axs3_r[n]}}, axs3_r};

// ------------------------- * F6 *
	wire [n:0]fxs0_r,cxs1_r,cxs2_r,fxs3_r;

	B4DM2 B4DM28(.A(S0),.B(f),.S(fxs0_r));
	B4DM2 B4DM29(.A(S1),.B(c),.S(cxs1_r));
	B4DM2 B4DM210(.A(S2),.B(c),.S(cxs2_r));
	B4DM2 B4DM211(.A(S3),.B(f),.S(fxs3_r));

	assign F6 = {{3{fxs0_r[n]}}, fxs0_r} - {{3{cxs1_r[n]}}, cxs1_r} + {{3{cxs2_r[n]}}, cxs2_r} - {{3{fxs3_r[n]}}, fxs3_r};

//b  d  e  g s4 F1
//d -g -b -e s6 F3
//e -b -g  d s6 F5
//g -e  d -b s7 F7 

// ------------------------- * F1 *
	wire [n:0]bxs4_r,dxs5_r,exs6_r,gxs7_r;
	
	B4DM2 B4DM212(.A(S4),.B(b),.S(bxs4_r));
	B4DM2 B4DM213(.A(S5),.B(d),.S(dxs5_r));
	B4DM2 B4DM214(.A(S6),.B(e),.S(exs6_r));
	B4DM2 B4DM215(.A(S7),.B(g),.S(gxs7_r));

	assign F1 = {{3{bxs4_r[n]}}, bxs4_r} + {{3{dxs5_r[n]}}, dxs5_r} + {{3{exs6_r[n]}}, exs6_r} + {{3{gxs7_r[n]}}, gxs7_r};		
	
// ------------------------- * F3 *	
	wire [n:0]dxs4_r,gxs5_r,bxs6_r,exs7_r;

	B4DM2 B4DM216(.A(S4),.B(d),.S(dxs4_r));
	B4DM2 B4DM217(.A(S5),.B(g),.S(gxs5_r));
	B4DM2 B4DM218(.A(S6),.B(b),.S(bxs6_r));
	B4DM2 B4DM219(.A(S7),.B(e),.S(exs7_r));
	
	assign F3 = {{3{dxs4_r[n]}}, dxs4_r} - {{3{gxs5_r[n]}}, gxs5_r} - {{3{bxs6_r[n]}}, bxs6_r} - {{3{exs7_r[n]}}, exs7_r};	

// ------------------------- * F5 *
	wire [n:0]exs4_r,bxs5_r,gxs6_r,dxs7_r;	
	
	B4DM2 B4DM220(.A(S4),.B(e),.S(exs4_r));
	B4DM2 B4DM221(.A(S5),.B(b),.S(bxs5_r));
	B4DM2 B4DM222(.A(S6),.B(g),.S(gxs6_r));
	B4DM2 B4DM223(.A(S7),.B(d),.S(dxs7_r));	

	assign F5 = {{3{exs4_r[n]}}, exs4_r} - {{3{bxs5_r[n]}}, bxs5_r} + {{3{gxs6_r[n]}}, gxs6_r} + {{3{dxs7_r[n]}}, dxs7_r};		
	
// ------------------------- * F7 *	
	wire [n:0]gxs4_r,exs5_r,dxs6_r,bxs7_r;	
	
	B4DM2 B4DM224(.A(S4),.B(g),.S(gxs4_r));
	B4DM2 B4DM225(.A(S5),.B(e),.S(exs5_r));
	B4DM2 B4DM226(.A(S6),.B(d),.S(dxs6_r));
	B4DM2 B4DM227(.A(S7),.B(b),.S(bxs7_r));		

	assign F7 = {{3{gxs4_r[n]}}, gxs4_r} - {{3{exs5_r[n]}}, exs5_r} + {{3{dxs6_r[n]}}, dxs6_r} - {{3{bxs7_r[n]}}, bxs7_r};	

endmodule