📄 digital6counter.map.rpt
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Analysis & Synthesis report for Digital6Counter
Sat Mar 24 23:23:43 2007
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
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1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. Parameter Settings for User Entity Instance: counter:inst1
8. Parameter Settings for User Entity Instance: counter:inst11
9. Parameter Settings for User Entity Instance: counter:inst
10. Parameter Settings for User Entity Instance: choice1from6:inst8
11. Parameter Settings for User Entity Instance: counter:inst2
12. Parameter Settings for User Entity Instance: counter:inst3
13. Parameter Settings for User Entity Instance: counter:inst4
14. Parameter Settings for User Entity Instance: counter:inst5
15. Parameter Settings for User Entity Instance: counter:inst7
16. Parameter Settings for User Entity Instance: counter:inst6
17. Parameter Settings for Inferred Entity Instance: counter:inst11|lpm_add_sub:add_rtl_0
18. Parameter Settings for Inferred Entity Instance: counter:inst|lpm_add_sub:add_rtl_1
19. Analysis & Synthesis Equations
20. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sat Mar 24 23:23:43 2007 ;
; Quartus II Version ; 5.1 Build 176 10/26/2005 SJ Full Version ;
; Revision Name ; Digital6Counter ;
; Top-level Entity Name ; DigitalClock ;
; Family ; MAX3000A ;
; Total macrocells ; 119 ;
; Total pins ; 24 ;
+-----------------------------+------------------------------------------+
+-----------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------+------------------+-----------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------+------------------+-----------------+
; Device ; EPM3128ATC100-10 ; ;
; Top-level entity name ; DigitalClock ; Digital6Counter ;
; Family name ; MAX3000A ; Stratix ;
; Use smart compilation ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Auto ; Auto ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Off ; Off ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A ; Speed ; Speed ;
; Allow XOR Gate Usage ; On ; On ;
; Auto Logic Cell Insertion ; On ; On ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4 ; 4 ;
; Auto Parallel Expanders ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A ; 100 ; 100 ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
+----------------------------------------------------------------------+------------------+-----------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+
; counter.vhd ; yes ; User VHDL File ; H:/03-源码文件/VHDL/03-数字钟/counter.vhd ;
; leddrv.vhd ; yes ; User VHDL File ; H:/03-源码文件/VHDL/03-数字钟/leddrv.vhd ;
; choice1from6.vhd ; yes ; User VHDL File ; H:/03-源码文件/VHDL/03-数字钟/choice1from6.vhd ;
; seg7_leddrv.vhd ; yes ; User VHDL File ; H:/03-源码文件/VHDL/03-数字钟/seg7_leddrv.vhd ;
; DigitalClock.bdf ; yes ; User Block Diagram/Schematic File ; H:/03-源码文件/VHDL/03-数字钟/DigitalClock.bdf ;
; lpm_add_sub.tdf ; yes ; Megafunction ; f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf ;
; addcore.inc ; yes ; Other ; f:/altera/quartus51/libraries/megafunctions/addcore.inc ;
; look_add.inc ; yes ; Other ; f:/altera/quartus51/libraries/megafunctions/look_add.inc ;
; bypassff.inc ; yes ; Other ; f:/altera/quartus51/libraries/megafunctions/bypassff.inc ;
; altshift.inc ; yes ; Other ; f:/altera/quartus51/libraries/megafunctions/altshift.inc ;
; alt_stratix_add_sub.inc ; yes ; Other ; f:/altera/quartus51/libraries/megafunctions/alt_stratix_add_sub.inc ;
; alt_mercury_add_sub.inc ; yes ; Other ; f:/altera/quartus51/libraries/megafunctions/alt_mercury_add_sub.inc ;
; aglobal51.inc ; yes ; Other ; f:/altera/quartus51/libraries/megafunctions/aglobal51.inc ;
; addcore.tdf ; yes ; Megafunction ; f:/altera/quartus51/libraries/megafunctions/addcore.tdf ;
; a_csnbuffer.inc ; yes ; Other ; f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.inc ;
; a_csnbuffer.tdf ; yes ; Megafunction ; f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf ;
; altshift.tdf ; yes ; Megafunction ; f:/altera/quartus51/libraries/megafunctions/altshift.tdf ;
; look_add.tdf ; yes ; Megafunction ; f:/altera/quartus51/libraries/megafunctions/look_add.tdf ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 119 ;
; Total registers ; 97 ;
; I/O pins ; 24 ;
; Parallel expanders ; 6 ;
; Maximum fan-out node ; reset ;
; Maximum fan-out ; 113 ;
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