sram.txt

用vhdl格式写的sram源代码

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
entity sram is 
  port(sysclk:in std_logic;
       WE:out std_logic;
       OE:out std_logic;
       LB:out std_logic;
       HB:out std_logic;
       CE:out std_logic;
       A1:out std_logic;
       A0:out std_logic;
       E:out std_logic;
       data:inout std_logic_vector(15 downto 0);
       address:out std_logic_vector(17 downto 0);
       datatemp:out std_logic_vector(15 downto 0));
  end sram;
 architecture tcl of sram is
  type state is(prepare,transmit_write_address,transmit_data,write_data,
                transmit_read_address,read_data,stop);
  signal current_state:state;
  signal clk:std_logic;
 begin
  A1<='0';
  A0<='0';
  E<='1';
  pulse:process(sysclk)
   variable count:integer range 0 to 10;
      begin
          if(sysclk'event and sysclk='1')then count:=count+1;
               if(count=5)then clk<='1';
               elsif (count=10) then
               clk<='0';
               count:=0;
               end if;
           end if;
     end process;

  process(clk)
    variable count1:integer range 0 to 100;
      begin
         if(clk'event and clk='1')then
              case current_state is
                   when prepare=>count1:=count1+1;OE<='0';CE<='0';
                         if(count1=50)then current_state<=transmit_write_address;count1:=0;
                         else current_state<=prepare;
                         end if;
                   when transmit_write_address=>count1:=count1+1;address<="000000000000000000";
                         if(count1=10)then current_state<=write_data;count1:=0;
                         else current_state<=transmit_write_address;
                         end if;
                    when write_data=>data<="1111110000000000";count1:=count1+1;
                          if(count1<3)then WE<='1';LB<='1';HB<='1';
                          elsif(count1<10)then WE<='0';LB<='0';HB<='0';
                          elsif(count1=11)then WE<='1';LB<='1';HB<='1';current_state<=transmit_read_address;
                                              count1:=0;
                          end if;
                    when transmit_read_address=>address<="000000000000000000";count1:=count1+1;
                         if(count1=2)then current_state<=read_data;count1:=0;data<="ZZZZZZZZZZZZZZZZ";WE<='1';LB<='0';HB<='0';
                         end if;
                     when read_data=>count1:=count1+1;
                          if(count1=2)then datatemp<=data;current_state<=stop;
                          else current_state<=read_data;
                           end if;
                     when stop=>NULL;
                     when others=>NULL;
                  end case;
             end if;
          end process;
   end tcl;