div12.tan.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register cnt\[2\] clk_temp 340.02 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 340.02 MHz between source register \"cnt\[2\]\" and destination register \"clk_temp\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.941 ns " "Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.224 ns + Longest register register " "Info: + Longest register to register delay is 1.224 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[2\] 1 REG LCFF_X1_Y6_N11 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y6_N11; Fanout = 3; REG Node = 'cnt\[2\]'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[2] } "NODE_NAME" } } { "div12.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/QuartusII/QuartusII/VHDL/VHDL/my_eda(3-7)/div12/div12.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.465 ns) + CELL(0.651 ns) 1.116 ns clk_temp~23 2 COMB LCCOMB_X1_Y6_N12 1 " "Info: 2: + IC(0.465 ns) + CELL(0.651 ns) = 1.116 ns; Loc. = LCCOMB_X1_Y6_N12; Fanout = 1; COMB Node = 'clk_temp~23'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "1.116 ns" { cnt[2] clk_temp~23 } "NODE_NAME" } } { "div12.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/QuartusII/QuartusII/VHDL/VHDL/my_eda(3-7)/div12/div12.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.224 ns clk_temp 3 REG LCFF_X1_Y6_N13 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.224 ns; Loc. = LCFF_X1_Y6_N13; Fanout = 2; REG Node = 'clk_temp'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { clk_temp~23 clk_temp } "NODE_NAME" } } { "div12.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/QuartusII/QuartusII/VHDL/VHDL/my_eda(3-7)/div12/div12.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.759 ns ( 62.01 % ) " "Info: Total cell delay = 0.759 ns ( 62.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.465 ns ( 37.99 % ) " "Info: Total interconnect delay = 0.465 ns ( 37.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "1.224 ns" { cnt[2] clk_temp~23 clk_temp } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "1.224 ns" { cnt[2] {} clk_temp~23 {} clk_temp {} } { 0.000ns 0.465ns 0.000ns } { 0.000ns 0.651ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.801 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.801 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div12.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/QuartusII/QuartusII/VHDL/VHDL/my_eda(3-7)/div12/div12.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 4 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "div12.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/QuartusII/QuartusII/VHDL/VHDL/my_eda(3-7)/div12/div12.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.906 ns) + CELL(0.666 ns) 2.801 ns clk_temp 3 REG LCFF_X1_Y6_N13 2 " "Info: 3: + IC(0.906 ns) + CELL(0.666 ns) = 2.801 ns; Loc. = LCFF_X1_Y6_N13; Fanout = 2; REG Node = 'clk_temp'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "1.572 ns" { clk~clkctrl clk_temp } "NODE_NAME" } } { "div12.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/QuartusII/QuartusII/VHDL/VHDL/my_eda(3-7)/div12/div12.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.69 % ) " "Info: Total cell delay = 1.756 ns ( 62.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.045 ns ( 37.31 % ) " "Info: Total interconnect delay = 1.045 ns ( 37.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "2.801 ns" { clk clk~clkctrl clk_temp } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "2.801 ns" { clk {} clk~combout {} clk~clkctrl {} clk_temp {} } { 0.000ns 0.000ns 0.139ns 0.906ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.801 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.801 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div12.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/QuartusII/QuartusII/VHDL/VHDL/my_eda(3-7)/div12/div12.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 4 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "div12.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/QuartusII/QuartusII/VHDL/VHDL/my_eda(3-7)/div12/div12.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.906 ns) + CELL(0.666 ns) 2.801 ns cnt\[2\] 3 REG LCFF_X1_Y6_N11 3 " "Info: 3: + IC(0.906 ns) + CELL(0.666 ns) = 2.801 ns; Loc. = LCFF_X1_Y6_N11; Fanout = 3; REG Node = 'cnt\[2\]'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "1.572 ns" { clk~clkctrl cnt[2] } "NODE_NAME" } } { "div12.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/QuartusII/QuartusII/VHDL/VHDL/my_eda(3-7)/div12/div12.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.69 % ) " "Info: Total cell delay = 1.756 ns ( 62.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.045 ns ( 37.31 % ) " "Info: Total interconnect delay = 1.045 ns ( 37.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "2.801 ns" { clk clk~clkctrl cnt[2] } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "2.801 ns" { clk {} clk~combout {} clk~clkctrl {} cnt[2] {} } { 0.000ns 0.000ns 0.139ns 0.906ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "2.801 ns" { clk clk~clkctrl clk_temp } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "2.801 ns" { clk {} clk~combout {} clk~clkctrl {} clk_temp {} } { 0.000ns 0.000ns 0.139ns 0.906ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "2.801 ns" { clk clk~clkctrl cnt[2] } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "2.801 ns" { clk {} clk~combout {} clk~clkctrl {} cnt[2] {} } { 0.000ns 0.000ns 0.139ns 0.906ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "div12.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/QuartusII/QuartusII/VHDL/VHDL/my_eda(3-7)/div12/div12.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "div12.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/QuartusII/QuartusII/VHDL/VHDL/my_eda(3-7)/div12/div12.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "1.224 ns" { cnt[2] clk_temp~23 clk_temp } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "1.224 ns" { cnt[2] {} clk_temp~23 {} clk_temp {} } { 0.000ns 0.465ns 0.000ns } { 0.000ns 0.651ns 0.108ns } "" } } { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "2.801 ns" { clk clk~clkctrl clk_temp } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "2.801 ns" { clk {} clk~combout {} clk~clkctrl {} clk_temp {} } { 0.000ns 0.000ns 0.139ns 0.906ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "2.801 ns" { clk clk~clkctrl cnt[2] } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "2.801 ns" { clk {} clk~combout {} clk~clkctrl {} cnt[2] {} } { 0.000ns 0.000ns 0.139ns 0.906ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_temp } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { clk_temp {} } {  } {  } "" } } { "div12.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/QuartusII/QuartusII/VHDL/VHDL/my_eda(3-7)/div12/div12.vhd" 15 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk div12 clk_temp 6.865 ns register " "Info: tco from clock \"clk\" to destination pin \"div12\" through register \"clk_temp\" is 6.865 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.801 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.801 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div12.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/QuartusII/QuartusII/VHDL/VHDL/my_eda(3-7)/div12/div12.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 4 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "div12.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/QuartusII/QuartusII/VHDL/VHDL/my_eda(3-7)/div12/div12.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.906 ns) + CELL(0.666 ns) 2.801 ns clk_temp 3 REG LCFF_X1_Y6_N13 2 " "Info: 3: + IC(0.906 ns) + CELL(0.666 ns) = 2.801 ns; Loc. = LCFF_X1_Y6_N13; Fanout = 2; REG Node = 'clk_temp'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "1.572 ns" { clk~clkctrl clk_temp } "NODE_NAME" } } { "div12.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/QuartusII/QuartusII/VHDL/VHDL/my_eda(3-7)/div12/div12.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.69 % ) " "Info: Total cell delay = 1.756 ns ( 62.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.045 ns ( 37.31 % ) " "Info: Total interconnect delay = 1.045 ns ( 37.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "2.801 ns" { clk clk~clkctrl clk_temp } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "2.801 ns" { clk {} clk~combout {} clk~clkctrl {} clk_temp {} } { 0.000ns 0.000ns 0.139ns 0.906ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "div12.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/QuartusII/QuartusII/VHDL/VHDL/my_eda(3-7)/div12/div12.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.760 ns + Longest register pin " "Info: + Longest register to pin delay is 3.760 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_temp 1 REG LCFF_X1_Y6_N13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y6_N13; Fanout = 2; REG Node = 'clk_temp'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_temp } "NODE_NAME" } } { "div12.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/QuartusII/QuartusII/VHDL/VHDL/my_eda(3-7)/div12/div12.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.704 ns) + CELL(3.056 ns) 3.760 ns div12 2 PIN PIN_28 0 " "Info: 2: + IC(0.704 ns) + CELL(3.056 ns) = 3.760 ns; Loc. = PIN_28; Fanout = 0; PIN Node = 'div12'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "3.760 ns" { clk_temp div12 } "NODE_NAME" } } { "div12.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/QuartusII/QuartusII/VHDL/VHDL/my_eda(3-7)/div12/div12.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.056 ns ( 81.28 % ) " "Info: Total cell delay = 3.056 ns ( 81.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.704 ns ( 18.72 % ) " "Info: Total interconnect delay = 0.704 ns ( 18.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "3.760 ns" { clk_temp div12 } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "3.760 ns" { clk_temp {} div12 {} } { 0.000ns 0.704ns } { 0.000ns 3.056ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "2.801 ns" { clk clk~clkctrl clk_temp } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "2.801 ns" { clk {} clk~combout {} clk~clkctrl {} clk_temp {} } { 0.000ns 0.000ns 0.139ns 0.906ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "3.760 ns" { clk_temp div12 } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "3.760 ns" { clk_temp {} div12 {} } { 0.000ns 0.704ns } { 0.000ns 3.056ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "113 " "Info: Allocated 113 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 18 16:21:24 2008 " "Info: Processing ended: Wed Jun 18 16:21:24 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}