siso4_2.tan.rpt

大量VHDL写的数字系统设计有用实例达到

; Slack ; Required tsu ; Actual tsu ; From ; To   ; To Clock ;
+-------+--------------+------------+------+------+----------+
; N/A   ; None         ; 4.267 ns   ; din  ; q[0] ; clk      ;
+-------+--------------+------------+------+------+----------+


+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+-----------+------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To   ; From Clock ;
+-------+--------------+------------+-----------+------+------------+
; N/A   ; None         ; 6.879 ns   ; dout~reg0 ; dout ; clk        ;
+-------+--------------+------------+-----------+------+------------+


+------------------------------------------------------------------+
; th                                                               ;
+---------------+-------------+-----------+------+------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To   ; To Clock ;
+---------------+-------------+-----------+------+------+----------+
; N/A           ; None        ; -4.001 ns ; din  ; q[0] ; clk      ;
+---------------+-------------+-----------+------+------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Mon Mar 19 15:59:13 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off siso4_2 -c siso4_2 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 340.02 MHz between source register "q[2]" and destination register "q[3]"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.747 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y18_N19; Fanout = 1; REG Node = 'q[2]'
            Info: 2: + IC(0.433 ns) + CELL(0.206 ns) = 0.639 ns; Loc. = LCCOMB_X1_Y18_N0; Fanout = 1; COMB Node = 'q[3]~feeder'
            Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.747 ns; Loc. = LCFF_X1_Y18_N1; Fanout = 1; REG Node = 'q[3]'
            Info: Total cell delay = 0.314 ns ( 42.03 % )
            Info: Total interconnect delay = 0.433 ns ( 57.97 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.815 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.815 ns; Loc. = LCFF_X1_Y18_N1; Fanout = 1; REG Node = 'q[3]'
                Info: Total cell delay = 1.756 ns ( 62.38 % )
                Info: Total interconnect delay = 1.059 ns ( 37.62 % )
            Info: - Longest clock path from clock "clk" to source register is 2.815 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.815 ns; Loc. = LCFF_X1_Y18_N19; Fanout = 1; REG Node = 'q[2]'
                Info: Total cell delay = 1.756 ns ( 62.38 % )
                Info: Total interconnect delay = 1.059 ns ( 37.62 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "q[0]" (data pin = "din", clock pin = "clk") is 4.267 ns
    Info: + Longest pin to register delay is 7.122 ns
        Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_142; Fanout = 1; PIN Node = 'din'
        Info: 2: + IC(5.718 ns) + CELL(0.460 ns) = 7.122 ns; Loc. = LCFF_X1_Y18_N7; Fanout = 1; REG Node = 'q[0]'
        Info: Total cell delay = 1.404 ns ( 19.71 % )
        Info: Total interconnect delay = 5.718 ns ( 80.29 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.815 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.815 ns; Loc. = LCFF_X1_Y18_N7; Fanout = 1; REG Node = 'q[0]'
        Info: Total cell delay = 1.756 ns ( 62.38 % )
        Info: Total interconnect delay = 1.059 ns ( 37.62 % )
Info: tco from clock "clk" to destination pin "dout" through register "dout~reg0" is 6.879 ns
    Info: + Longest clock path from clock "clk" to source register is 2.815 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.815 ns; Loc. = LCFF_X1_Y18_N13; Fanout = 1; REG Node = 'dout~reg0'
        Info: Total cell delay = 1.756 ns ( 62.38 % )
        Info: Total interconnect delay = 1.059 ns ( 37.62 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 3.760 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y18_N13; Fanout = 1; REG Node = 'dout~reg0'
        Info: 2: + IC(0.704 ns) + CELL(3.056 ns) = 3.760 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'dout'
        Info: Total cell delay = 3.056 ns ( 81.28 % )
        Info: Total interconnect delay = 0.704 ns ( 18.72 % )
Info: th for register "q[0]" (data pin = "din", clock pin = "clk") is -4.001 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.815 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.815 ns; Loc. = LCFF_X1_Y18_N7; Fanout = 1; REG Node = 'q[0]'
        Info: Total cell delay = 1.756 ns ( 62.38 % )
        Info: Total interconnect delay = 1.059 ns ( 37.62 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 7.122 ns
        Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_142; Fanout = 1; PIN Node = 'din'
        Info: 2: + IC(5.718 ns) + CELL(0.460 ns) = 7.122 ns; Loc. = LCFF_X1_Y18_N7; Fanout = 1; REG Node = 'q[0]'
        Info: Total cell delay = 1.404 ns ( 19.71 % )
        Info: Total interconnect delay = 5.718 ns ( 80.29 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Mar 19 15:59:14 2007
    Info: Elapsed time: 00:00:02