sipo.tan.rpt

大量VHDL写的数字系统设计有用实例达到

+-------+--------------+------------+------+------+----------+


+-----------------------------------------------------------------+
; tco                                                             ;
+-------+--------------+------------+------+---------+------------+
; Slack ; Required tco ; Actual tco ; From ; To      ; From Clock ;
+-------+--------------+------------+------+---------+------------+
; N/A   ; None         ; 7.877 ns   ; q[3] ; dout[3] ; clk        ;
; N/A   ; None         ; 7.582 ns   ; q[4] ; dout[4] ; clk        ;
; N/A   ; None         ; 7.556 ns   ; q[2] ; dout[2] ; clk        ;
; N/A   ; None         ; 7.493 ns   ; q[5] ; dout[4] ; clk        ;
; N/A   ; None         ; 7.493 ns   ; q[5] ; dout[3] ; clk        ;
; N/A   ; None         ; 7.271 ns   ; q[0] ; dout[0] ; clk        ;
; N/A   ; None         ; 7.246 ns   ; q[1] ; dout[1] ; clk        ;
; N/A   ; None         ; 7.203 ns   ; q[5] ; dout[0] ; clk        ;
; N/A   ; None         ; 7.180 ns   ; q[5] ; dout[2] ; clk        ;
; N/A   ; None         ; 7.180 ns   ; q[5] ; dout[1] ; clk        ;
+-------+--------------+------------+------+---------+------------+


+------------------------------------------------------------------+
; th                                                               ;
+---------------+-------------+-----------+------+------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To   ; To Clock ;
+---------------+-------------+-----------+------+------+----------+
; N/A           ; None        ; 1.201 ns  ; din  ; q[0] ; clk      ;
; N/A           ; None        ; 0.741 ns  ; clr  ; q[0] ; clk      ;
; N/A           ; None        ; 0.741 ns  ; clr  ; q[1] ; clk      ;
; N/A           ; None        ; 0.708 ns  ; clr  ; q[3] ; clk      ;
; N/A           ; None        ; 0.707 ns  ; clr  ; q[5] ; clk      ;
; N/A           ; None        ; 0.704 ns  ; clr  ; q[4] ; clk      ;
; N/A           ; None        ; 0.704 ns  ; clr  ; q[2] ; clk      ;
+---------------+-------------+-----------+------+------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Mon Mar 19 22:37:47 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sipo -c sipo --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 340.02 MHz between source register "q[5]" and destination register "q[1]"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.057 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y9_N21; Fanout = 10; REG Node = 'q[5]'
            Info: 2: + IC(0.743 ns) + CELL(0.206 ns) = 0.949 ns; Loc. = LCCOMB_X1_Y9_N18; Fanout = 1; COMB Node = 'q~228'
            Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.057 ns; Loc. = LCFF_X1_Y9_N19; Fanout = 2; REG Node = 'q[1]'
            Info: Total cell delay = 0.314 ns ( 29.71 % )
            Info: Total interconnect delay = 0.743 ns ( 70.29 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.766 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.871 ns) + CELL(0.666 ns) = 2.766 ns; Loc. = LCFF_X1_Y9_N19; Fanout = 2; REG Node = 'q[1]'
                Info: Total cell delay = 1.756 ns ( 63.49 % )
                Info: Total interconnect delay = 1.010 ns ( 36.51 % )
            Info: - Longest clock path from clock "clk" to source register is 2.766 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.871 ns) + CELL(0.666 ns) = 2.766 ns; Loc. = LCFF_X1_Y9_N21; Fanout = 10; REG Node = 'q[5]'
                Info: Total cell delay = 1.756 ns ( 63.49 % )
                Info: Total interconnect delay = 1.010 ns ( 36.51 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "q[4]" (data pin = "clr", clock pin = "clk") is -0.438 ns
    Info: + Longest pin to register delay is 2.368 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_21; Fanout = 6; PIN Node = 'clr'
        Info: 2: + IC(0.631 ns) + CELL(0.539 ns) = 2.260 ns; Loc. = LCCOMB_X1_Y9_N10; Fanout = 1; COMB Node = 'q~231'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.368 ns; Loc. = LCFF_X1_Y9_N11; Fanout = 2; REG Node = 'q[4]'
        Info: Total cell delay = 1.737 ns ( 73.35 % )
        Info: Total interconnect delay = 0.631 ns ( 26.65 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.766 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.871 ns) + CELL(0.666 ns) = 2.766 ns; Loc. = LCFF_X1_Y9_N11; Fanout = 2; REG Node = 'q[4]'
        Info: Total cell delay = 1.756 ns ( 63.49 % )
        Info: Total interconnect delay = 1.010 ns ( 36.51 % )
Info: tco from clock "clk" to destination pin "dout[3]" through register "q[3]" is 7.877 ns
    Info: + Longest clock path from clock "clk" to source register is 2.766 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.871 ns) + CELL(0.666 ns) = 2.766 ns; Loc. = LCFF_X1_Y9_N23; Fanout = 2; REG Node = 'q[3]'
        Info: Total cell delay = 1.756 ns ( 63.49 % )
        Info: Total interconnect delay = 1.010 ns ( 36.51 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 4.807 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y9_N23; Fanout = 2; REG Node = 'q[3]'
        Info: 2: + IC(1.751 ns) + CELL(3.056 ns) = 4.807 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'dout[3]'
        Info: Total cell delay = 3.056 ns ( 63.57 % )
        Info: Total interconnect delay = 1.751 ns ( 36.43 % )
Info: th for register "q[0]" (data pin = "din", clock pin = "clk") is 1.201 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.766 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.871 ns) + CELL(0.666 ns) = 2.766 ns; Loc. = LCFF_X1_Y9_N17; Fanout = 2; REG Node = 'q[0]'
        Info: Total cell delay = 1.756 ns ( 63.49 % )
        Info: Total interconnect delay = 1.010 ns ( 36.51 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 1.871 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; PIN Node = 'din'
        Info: 2: + IC(0.467 ns) + CELL(0.206 ns) = 1.763 ns; Loc. = LCCOMB_X1_Y9_N16; Fanout = 1; COMB Node = 'q~226'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.871 ns; Loc. = LCFF_X1_Y9_N17; Fanout = 2; REG Node = 'q[0]'
        Info: Total cell delay = 1.404 ns ( 75.04 % )
        Info: Total interconnect delay = 0.467 ns ( 24.96 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Mar 19 22:37:47 2007
    Info: Elapsed time: 00:00:02