reg8.fit.rpt

大量VHDL写的数字系统设计有用实例达到

; R4 interconnects           ; 12 / 22,440 ( < 1 % ) ;
+----------------------------+-----------------------+


+--------------------------------------------------------------------------+
; LAB Logic Elements                                                       ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements  (Average = 1.00) ; Number of LABs  (Total = 8) ;
+--------------------------------------------+-----------------------------+
; 1                                          ; 8                           ;
; 2                                          ; 0                           ;
; 3                                          ; 0                           ;
; 4                                          ; 0                           ;
; 5                                          ; 0                           ;
; 6                                          ; 0                           ;
; 7                                          ; 0                           ;
; 8                                          ; 0                           ;
; 9                                          ; 0                           ;
; 10                                         ; 0                           ;
; 11                                         ; 0                           ;
; 12                                         ; 0                           ;
; 13                                         ; 0                           ;
; 14                                         ; 0                           ;
; 15                                         ; 0                           ;
; 16                                         ; 0                           ;
+--------------------------------------------+-----------------------------+


+------------------------------------------------------------------+
; LAB-wide Signals                                                 ;
+------------------------------------+-----------------------------+
; LAB-wide Signals  (Average = 1.00) ; Number of LABs  (Total = 8) ;
+------------------------------------+-----------------------------+
; 1 Clock                            ; 8                           ;
+------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Signals Sourced                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced  (Average = 1.50) ; Number of LABs  (Total = 8) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 4                           ;
; 2                                           ; 4                           ;
+---------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                       ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out  (Average = 1.00) ; Number of LABs  (Total = 8) ;
+-------------------------------------------------+-----------------------------+
; 0                                               ; 0                           ;
; 1                                               ; 8                           ;
+-------------------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Distinct Inputs                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs  (Average = 2.00) ; Number of LABs  (Total = 8) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 0                           ;
; 2                                           ; 8                           ;
+---------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Active Serial            ;
; Error detection CRC                          ; Off                      ;
; Reserve nCEO pin after configuration         ; As output driving ground ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Fri Mar 16 14:51:28 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off reg8 -c reg8
Info: Selected device EP2C8T144C8 for design "reg8"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C5T144C8 is compatible
    Info: Device EP2C5T144I8 is compatible
    Info: Device EP2C8T144I8 is compatible
Info: No exact pin location assignment(s) for 18 pins of 18 total pins
    Info: Pin Q[7] not assigned to an exact location on the device
    Info: Pin Q[6] not assigned to an exact location on the device
    Info: Pin Q[5] not assigned to an exact location on the device
    Info: Pin Q[4] not assigned to an exact location on the device
    Info: Pin Q[3] not assigned to an exact location on the device
    Info: Pin Q[2] not assigned to an exact location on the device
    Info: Pin Q[1] not assigned to an exact location on the device
    Info: Pin Q[0] not assigned to an exact location on the device
    Info: Pin OE not assigned to an exact location on the device
    Info: Pin D[7] not assigned to an exact location on the device
    Info: Pin CLK not assigned to an exact location on the device
    Info: Pin D[6] not assigned to an exact location on the device
    Info: Pin D[5] not assigned to an exact location on the device
    Info: Pin D[4] not assigned to an exact location on the device
    Info: Pin D[3] not assigned to an exact location on the device
    Info: Pin D[2] not assigned to an exact location on the device
    Info: Pin D[1] not assigned to an exact location on the device
    Info: Pin D[0] not assigned to an exact location on the device
Info: Automatically promoted node CLK (placed in PIN 17 (CLK0, LVDSCLK0p, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pi