div_half.fit.smsg

大量VHDL写的数字系统设计有用实例达到

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sat Mar 31 21:22:34 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off div_half -c div_half
Info: Selected device EP2C8T144C8 for design "div_half"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C5T144C8 is compatible
    Info: Device EP2C5T144I8 is compatible
    Info: Device EP2C8T144I8 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location 1
    Info: Pin ~nCSO~ is reserved at location 2
    Info: Pin ~LVDS54p/nCEO~ is reserved at location 76
Warning: No exact pin location assignment(s) for 2 pins of 2 total pins
    Info: Pin div not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
Info: Automatically promoted node clk_temp1 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 2 (unused VREF, 3.30 VCCIO, 1 input, 1 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  15 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  23 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  20 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 6.316 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X13_Y18; Fanout = 3; REG Node = 'count[1]'
    Info: 2: + IC(0.954 ns) + CELL(0.621 ns) = 1.575 ns; Loc. = LAB_X14_Y18; Fanout = 2; COMB Node = 'Add0~419'
    Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.661 ns; Loc. = LAB_X14_Y18; Fanout = 2; COMB Node = 'Add0~421'
    Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.747 ns; Loc. = LAB_X14_Y18; Fanout = 2; COMB Node = 'Add0~423'
    Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.833 ns; Loc. = LAB_X14_Y18; Fanout = 2; COMB Node = 'Add0~425'
    Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.919 ns; Loc. = LAB_X14_Y18; Fanout = 2; COMB Node = 'Add0~427'
    Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 2.005 ns; Loc. = LAB_X14_Y18; Fanout = 2; COMB Node = 'Add0~429'
    Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 2.091 ns; Loc. = LAB_X14_Y18; Fanout = 2; COMB Node = 'Add0~431'
    Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 2.177 ns; Loc. = LAB_X14_Y18; Fanout = 2; COMB Node = 'Add0~433'
    Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 2.263 ns; Loc. = LAB_X14_Y18; Fanout = 2; COMB Node = 'Add0~435'
    Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.349 ns; Loc. = LAB_X14_Y18; Fanout = 2; COMB Node = 'Add0~437'
    Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.435 ns; Loc. = LAB_X14_Y18; Fanout = 2; COMB Node = 'Add0~439'
    Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.521 ns; Loc. = LAB_X14_Y18; Fanout = 2; COMB Node = 'Add0~441'
    Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 2.607 ns; Loc. = LAB_X14_Y18; Fanout = 2; COMB Node = 'Add0~443'
    Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 2.693 ns; Loc. = LAB_X14_Y18; Fanout = 2; COMB Node = 'Add0~445'
    Info: 16: + IC(0.000 ns) + CELL(0.086 ns) = 2.779 ns; Loc. = LAB_X14_Y18; Fanout = 2; COMB Node = 'Add0~447'
    Info: 17: + IC(0.107 ns) + CELL(0.086 ns) = 2.972 ns; Loc. = LAB_X14_Y17; Fanout = 2; COMB Node = 'Add0~449'
    Info: 18: + IC(0.000 ns) + CELL(0.086 ns) = 3.058 ns; Loc. = LAB_X14_Y17; Fanout = 2; COMB Node = 'Add0~451'
    Info: 19: + IC(0.000 ns) + CELL(0.086 ns) = 3.144 ns; Loc. = LAB_X14_Y17; Fanout = 2; COMB Node = 'Add0~453'
    Info: 20: + IC(0.000 ns) + CELL(0.086 ns) = 3.230 ns; Loc. = LAB_X14_Y17; Fanout = 2; COMB Node = 'Add0~455'
    Info: 21: + IC(0.000 ns) + CELL(0.086 ns) = 3.316 ns; Loc. = LAB_X14_Y17; Fanout = 2; COMB Node = 'Add0~457'
    Info: 22: + IC(0.000 ns) + CELL(0.086 ns) = 3.402 ns; Loc. = LAB_X14_Y17; Fanout = 2; COMB Node = 'Add0~459'
    Info: 23: + IC(0.000 ns) + CELL(0.086 ns) = 3.488 ns; Loc. = LAB_X14_Y17; Fanout = 2; COMB Node = 'Add0~461'
    Info: 24: + IC(0.000 ns) + CELL(0.086 ns) = 3.574 ns; Loc. = LAB_X14_Y17; Fanout = 2; COMB Node = 'Add0~463'
    Info: 25: + IC(0.000 ns) + CELL(0.086 ns) = 3.660 ns; Loc. = LAB_X14_Y17; Fanout = 2; COMB Node = 'Add0~465'
    Info: 26: + IC(0.000 ns) + CELL(0.086 ns) = 3.746 ns; Loc. = LAB_X14_Y17; Fanout = 2; COMB Node = 'Add0~467'
    Info: 27: + IC(0.000 ns) + CELL(0.086 ns) = 3.832 ns; Loc. = LAB_X14_Y17; Fanout = 2; COMB Node = 'Add0~469'
    Info: 28: + IC(0.000 ns) + CELL(0.086 ns) = 3.918 ns; Loc. = LAB_X14_Y17; Fanout = 2; COMB Node = 'Add0~471'
    Info: 29: + IC(0.000 ns) + CELL(0.086 ns) = 4.004 ns; Loc. = LAB_X14_Y17; Fanout = 2; COMB Node = 'Add0~473'
    Info: 30: + IC(0.000 ns) + CELL(0.086 ns) = 4.090 ns; Loc. = LAB_X14_Y17; Fanout = 2; COMB Node = 'Add0~475'
    Info: 31: + IC(0.000 ns) + CELL(0.086 ns) = 4.176 ns; Loc. = LAB_X14_Y17; Fanout = 1; COMB Node = 'Add0~477'
    Info: 32: + IC(0.000 ns) + CELL(0.506 ns) = 4.682 ns; Loc. = LAB_X14_Y17; Fanout = 1; COMB Node = 'Add0~478'
    Info: 33: + IC(0.875 ns) + CELL(0.651 ns) = 6.208 ns; Loc. = LAB_X15_Y18; Fanout = 1; COMB Node = 'count~438'
    Info: 34: + IC(0.000 ns) + CELL(0.108 ns) = 6.316 ns; Loc. = LAB_X15_Y18; Fanout = 2; REG Node = 'count[31]'
    Info: Total cell delay = 4.380 ns ( 69.35 % )
    Info: Total interconnect delay = 1.936 ns ( 30.65 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X11_Y10 to location X22_Y19
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 1 output pins without output pin load capacitance assignment
    Info: Pin "div" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 173 megabytes of memory during processing
    Info: Processing ended: Sat Mar 31 21:22:43 2007
    Info: Elapsed time: 00:00:09