div_half.tan.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Info" "ITDB_FULL_TCO_RESULT" "clk div div~reg0 10.875 ns register " "Info: tco from clock \"clk\" to destination pin \"div\" through register \"div~reg0\" is 10.875 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.440 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 6.440 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns clk 1 CLK PIN_25 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_25; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.934 ns) + CELL(0.206 ns) 3.085 ns clk_temp1 2 COMB LCCOMB_X15_Y10_N0 1 " "Info: 2: + IC(1.934 ns) + CELL(0.206 ns) = 3.085 ns; Loc. = LCCOMB_X15_Y10_N0; Fanout = 1; COMB Node = 'clk_temp1'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.140 ns" { clk clk_temp1 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.751 ns) + CELL(0.000 ns) 4.836 ns clk_temp1~clkctrl 3 COMB CLKCTRL_G4 33 " "Info: 3: + IC(1.751 ns) + CELL(0.000 ns) = 4.836 ns; Loc. = CLKCTRL_G4; Fanout = 33; COMB Node = 'clk_temp1~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.751 ns" { clk_temp1 clk_temp1~clkctrl } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.938 ns) + CELL(0.666 ns) 6.440 ns div~reg0 4 REG LCFF_X15_Y18_N3 2 " "Info: 4: + IC(0.938 ns) + CELL(0.666 ns) = 6.440 ns; Loc. = LCFF_X15_Y18_N3; Fanout = 2; REG Node = 'div~reg0'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.604 ns" { clk_temp1~clkctrl div~reg0 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 18 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.817 ns ( 28.21 % ) " "Info: Total cell delay = 1.817 ns ( 28.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.623 ns ( 71.79 % ) " "Info: Total interconnect delay = 4.623 ns ( 71.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.440 ns" { clk clk_temp1 clk_temp1~clkctrl div~reg0 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.440 ns" { clk clk~combout clk_temp1 clk_temp1~clkctrl div~reg0 } { 0.000ns 0.000ns 1.934ns 1.751ns 0.938ns } { 0.000ns 0.945ns 0.206ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 18 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.131 ns + Longest register pin " "Info: + Longest register to pin delay is 4.131 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns div~reg0 1 REG LCFF_X15_Y18_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y18_N3; Fanout = 2; REG Node = 'div~reg0'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { div~reg0 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 18 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.915 ns) + CELL(3.216 ns) 4.131 ns div 2 PIN PIN_129 0 " "Info: 2: + IC(0.915 ns) + CELL(3.216 ns) = 4.131 ns; Loc. = PIN_129; Fanout = 0; PIN Node = 'div'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.131 ns" { div~reg0 div } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.216 ns ( 77.85 % ) " "Info: Total cell delay = 3.216 ns ( 77.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.915 ns ( 22.15 % ) " "Info: Total interconnect delay = 0.915 ns ( 22.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.131 ns" { div~reg0 div } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.131 ns" { div~reg0 div } { 0.000ns 0.915ns } { 0.000ns 3.216ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.440 ns" { clk clk_temp1 clk_temp1~clkctrl div~reg0 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.440 ns" { clk clk~combout clk_temp1 clk_temp1~clkctrl div~reg0 } { 0.000ns 0.000ns 1.934ns 1.751ns 0.938ns } { 0.000ns 0.945ns 0.206ns 0.000ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.131 ns" { div~reg0 div } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.131 ns" { div~reg0 div } { 0.000ns 0.915ns } { 0.000ns 3.216ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "101 " "Info: Allocated 101 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 31 21:23:01 2007 " "Info: Processing ended: Sat Mar 31 21:23:01 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}