📄 div_half.tan.qmsg

📁 大量VHDL写的数字系统设计有用实例达到
💻 QMSG
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 6 -1 0 } } { "e:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk_temp2 " "Info: Detected ripple clock \"clk_temp2\" as buffer" {  } { { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 12 -1 0 } } { "e:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_temp2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "clk_temp1 " "Info: Detected gated clock \"clk_temp1\" as buffer" {  } { { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 11 -1 0 } } { "e:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_temp1" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div~reg0 " "Info: Detected ripple clock \"div~reg0\" as buffer" {  } { { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 18 0 0 } } { "e:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "div~reg0" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count\[1\] register count\[29\] 156.76 MHz 6.379 ns Internal " "Info: Clock \"clk\" has Internal fmax of 156.76 MHz between source register \"count\[1\]\" and destination register \"count\[29\]\" (period= 6.379 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.115 ns + Longest register register " "Info: + Longest register to register delay is 6.115 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[1\] 1 REG LCFF_X13_Y18_N19 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X13_Y18_N19; Fanout = 3; REG Node = 'count\[1\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { count[1] } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.755 ns) + CELL(0.596 ns) 1.351 ns Add0~419 2 COMB LCCOMB_X14_Y18_N2 2 " "Info: 2: + IC(0.755 ns) + CELL(0.596 ns) = 1.351 ns; Loc. = LCCOMB_X14_Y18_N2; Fanout = 2; COMB Node = 'Add0~419'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.351 ns" { count[1] Add0~419 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.437 ns Add0~421 3 COMB LCCOMB_X14_Y18_N4 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.437 ns; Loc. = LCCOMB_X14_Y18_N4; Fanout = 2; COMB Node = 'Add0~421'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~419 Add0~421 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.523 ns Add0~423 4 COMB LCCOMB_X14_Y18_N6 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.523 ns; Loc. = LCCOMB_X14_Y18_N6; Fanout = 2; COMB Node = 'Add0~423'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~421 Add0~423 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.609 ns Add0~425 5 COMB LCCOMB_X14_Y18_N8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.609 ns; Loc. = LCCOMB_X14_Y18_N8; Fanout = 2; COMB Node = 'Add0~425'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~423 Add0~425 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.695 ns Add0~427 6 COMB LCCOMB_X14_Y18_N10 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.695 ns; Loc. = LCCOMB_X14_Y18_N10; Fanout = 2; COMB Node = 'Add0~427'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~425 Add0~427 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.781 ns Add0~429 7 COMB LCCOMB_X14_Y18_N12 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 1.781 ns; Loc. = LCCOMB_X14_Y18_N12; Fanout = 2; COMB Node = 'Add0~429'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~427 Add0~429 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 1.971 ns Add0~431 8 COMB LCCOMB_X14_Y18_N14 2 " "Info: 8: + IC(0.000 ns) + CELL(0.190 ns) = 1.971 ns; Loc. = LCCOMB_X14_Y18_N14; Fanout = 2; COMB Node = 'Add0~431'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.190 ns" { Add0~429 Add0~431 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.057 ns Add0~433 9 COMB LCCOMB_X14_Y18_N16 2 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 2.057 ns; Loc. = LCCOMB_X14_Y18_N16; Fanout = 2; COMB Node = 'Add0~433'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~431 Add0~433 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.143 ns Add0~435 10 COMB LCCOMB_X14_Y18_N18 2 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 2.143 ns; Loc. = LCCOMB_X14_Y18_N18; Fanout = 2; COMB Node = 'Add0~435'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~433 Add0~435 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.229 ns Add0~437 11 COMB LCCOMB_X14_Y18_N20 2 " "Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.229 ns; Loc. = LCCOMB_X14_Y18_N20; Fanout = 2; COMB Node = 'Add0~437'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~435 Add0~437 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.315 ns Add0~439 12 COMB LCCOMB_X14_Y18_N22 2 " "Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.315 ns; Loc. = LCCOMB_X14_Y18_N22; Fanout = 2; COMB Node = 'Add0~439'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~437 Add0~439 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.401 ns Add0~441 13 COMB LCCOMB_X14_Y18_N24 2 " "Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.401 ns; Loc. = LCCOMB_X14_Y18_N24; Fanout = 2; COMB Node = 'Add0~441'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~439 Add0~441 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.487 ns Add0~443 14 COMB LCCOMB_X14_Y18_N26 2 " "Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 2.487 ns; Loc. = LCCOMB_X14_Y18_N26; Fanout = 2; COMB Node = 'Add0~443'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~441 Add0~443 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.573 ns Add0~445 15 COMB LCCOMB_X14_Y18_N28 2 " "Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 2.573 ns; Loc. = LCCOMB_X14_Y18_N28; Fanout = 2; COMB Node = 'Add0~445'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~443 Add0~445 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.175 ns) 2.748 ns Add0~447 16 COMB LCCOMB_X14_Y18_N30 2 " "Info: 16: + IC(0.000 ns) + CELL(0.175 ns) = 2.748 ns; Loc. = LCCOMB_X14_Y18_N30; Fanout = 2; COMB Node = 'Add0~447'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.175 ns" { Add0~445 Add0~447 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.834 ns Add0~449 17 COMB LCCOMB_X14_Y17_N0 2 " "Info: 17: + IC(0.000 ns) + CELL(0.086 ns) = 2.834 ns; Loc. = LCCOMB_X14_Y17_N0; Fanout = 2; COMB Node = 'Add0~449'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~447 Add0~449 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.920 ns Add0~451 18 COMB LCCOMB_X14_Y17_N2 2 " "Info: 18: + IC(0.000 ns) + CELL(0.086 ns) = 2.920 ns; Loc. = LCCOMB_X14_Y17_N2; Fanout = 2; COMB Node = 'Add0~451'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~449 Add0~451 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.006 ns Add0~453 19 COMB LCCOMB_X14_Y17_N4 2 " "Info: 19: + IC(0.000 ns) + CELL(0.086 ns) = 3.006 ns; Loc. = LCCOMB_X14_Y17_N4; Fanout = 2; COMB Node = 'Add0~453'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~451 Add0~453 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.092 ns Add0~455 20 COMB LCCOMB_X14_Y17_N6 2 " "Info: 20: + IC(0.000 ns) + CELL(0.086 ns) = 3.092 ns; Loc. = LCCOMB_X14_Y17_N6; Fanout = 2; COMB Node = 'Add0~455'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~453 Add0~455 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.178 ns Add0~457 21 COMB LCCOMB_X14_Y17_N8 2 " "Info: 21: + IC(0.000 ns) + CELL(0.086 ns) = 3.178 ns; Loc. = LCCOMB_X14_Y17_N8; Fanout = 2; COMB Node = 'Add0~457'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~455 Add0~457 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.264 ns Add0~459 22 COMB LCCOMB_X14_Y17_N10 2 " "Info: 22: + IC(0.000 ns) + CELL(0.086 ns) = 3.264 ns; Loc. = LCCOMB_X14_Y17_N10; Fanout = 2; COMB Node = 'Add0~459'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~457 Add0~459 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.350 ns Add0~461 23 COMB LCCOMB_X14_Y17_N12 2 " "Info: 23: + IC(0.000 ns) + CELL(0.086 ns) = 3.350 ns; Loc. = LCCOMB_X14_Y17_N12; Fanout = 2; COMB Node = 'Add0~461'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~459 Add0~461 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 3.540 ns Add0~463 24 COMB LCCOMB_X14_Y17_N14 2 " "Info: 24: + IC(0.000 ns) + CELL(0.190 ns) = 3.540 ns; Loc. = LCCOMB_X14_Y17_N14; Fanout = 2; COMB Node = 'Add0~463'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.190 ns" { Add0~461 Add0~463 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.626 ns Add0~465 25 COMB LCCOMB_X14_Y17_N16 2 " "Info: 25: + IC(0.000 ns) + CELL(0.086 ns) = 3.626 ns; Loc. = LCCOMB_X14_Y17_N16; Fanout = 2; COMB Node = 'Add0~465'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~463 Add0~465 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.712 ns Add0~467 26 COMB LCCOMB_X14_Y17_N18 2 " "Info: 26: + IC(0.000 ns) + CELL(0.086 ns) = 3.712 ns; Loc. = LCCOMB_X14_Y17_N18; Fanout = 2; COMB Node = 'Add0~467'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~465 Add0~467 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.798 ns Add0~469 27 COMB LCCOMB_X14_Y17_N20 2 " "Info: 27: + IC(0.000 ns) + CELL(0.086 ns) = 3.798 ns; Loc. = LCCOMB_X14_Y17_N20; Fanout = 2; COMB Node = 'Add0~469'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~467 Add0~469 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.884 ns Add0~471 28 COMB LCCOMB_X14_Y17_N22 2 " "Info: 28: + IC(0.000 ns) + CELL(0.086 ns) = 3.884 ns; Loc. = LCCOMB_X14_Y17_N22; Fanout = 2; COMB Node = 'Add0~471'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~469 Add0~471 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.970 ns Add0~473 29 COMB LCCOMB_X14_Y17_N24 2 " "Info: 29: + IC(0.000 ns) + CELL(0.086 ns) = 3.970 ns; Loc. = LCCOMB_X14_Y17_N24; Fanout = 2; COMB Node = 'Add0~473'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~471 Add0~473 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 4.476 ns Add0~474 30 COMB LCCOMB_X14_Y17_N26 1 " "Info: 30: + IC(0.000 ns) + CELL(0.506 ns) = 4.476 ns; Loc. = LCCOMB_X14_Y17_N26; Fanout = 1; COMB Node = 'Add0~474'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { Add0~473 Add0~474 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.325 ns) + CELL(0.206 ns) 6.007 ns count~436 31 COMB LCCOMB_X13_Y18_N28 1 " "Info: 31: + IC(1.325 ns) + CELL(0.206 ns) = 6.007 ns; Loc. = LCCOMB_X13_Y18_N28; Fanout = 1; COMB Node = 'count~436'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.531 ns" { Add0~474 count~436 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.115 ns count\[29\] 32 REG LCFF_X13_Y18_N29 3 " "Info: 32: + IC(0.000 ns) + CELL(0.108 ns) = 6.115 ns; Loc. = LCFF_X13_Y18_N29; Fanout = 3; REG Node = 'count\[29\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { count~436 count[29] } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.035 ns ( 65.99 % ) " "Info: Total cell delay = 4.035 ns ( 65.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.080 ns ( 34.01 % ) " "Info: Total interconnect delay = 2.080 ns ( 34.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.115 ns" { count[1] Add0~419 Add0~421 Add0~423 Add0~425 Add0~427 Add0~429 Add0~431 Add0~433 Add0~435 Add0~437 Add0~439 Add0~441 Add0~443 Add0~445 Add0~447 Add0~449 Add0~451 Add0~453 Add0~455 Add0~457 Add0~459 Add0~461 Add0~463 Add0~465 Add0~467 Add0~469 Add0~471 Add0~473 Add0~474 count~436 count[29] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.115 ns" { count[1] Add0~419 Add0~421 Add0~423 Add0~425 Add0~427 Add0~429 Add0~431 Add0~433 Add0~435 Add0~437 Add0~439 Add0~441 Add0~443 Add0~445 Add0~447 Add0~449 Add0~451 Add0~453 Add0~455 Add0~457 Add0~459 Add0~461 Add0~463 Add0~465 Add0~467 Add0~469 Add0~471 Add0~473 Add0~474 count~436 count[29] } { 0.000ns 0.755ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.325ns 0.000ns } { 0.000ns 0.596ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.438 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 6.438 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns clk 1 CLK PIN_25 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_25; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.934 ns) + CELL(0.206 ns) 3.085 ns clk_temp1 2 COMB LCCOMB_X15_Y10_N0 1 " "Info: 2: + IC(1.934 ns) + CELL(0.206 ns) = 3.085 ns; Loc. = LCCOMB_X15_Y10_N0; Fanout = 1; COMB Node = 'clk_temp1'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.140 ns" { clk clk_temp1 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.751 ns) + CELL(0.000 ns) 4.836 ns clk_temp1~clkctrl 3 COMB CLKCTRL_G4 33 " "Info: 3: + IC(1.751 ns) + CELL(0.000 ns) = 4.836 ns; Loc. = CLKCTRL_G4; Fanout = 33; COMB Node = 'clk_temp1~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.751 ns" { clk_temp1 clk_temp1~clkctrl } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.936 ns) + CELL(0.666 ns) 6.438 ns count\[29\] 4 REG LCFF_X13_Y18_N29 3 " "Info: 4: + IC(0.936 ns) + CELL(0.666 ns) = 6.438 ns; Loc. = LCFF_X13_Y18_N29; Fanout = 3; REG Node = 'count\[29\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.602 ns" { clk_temp1~clkctrl count[29] } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.817 ns ( 28.22 % ) " "Info: Total cell delay = 1.817 ns ( 28.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.621 ns ( 71.78 % ) " "Info: Total interconnect delay = 4.621 ns ( 71.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.438 ns" { clk clk_temp1 clk_temp1~clkctrl count[29] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.438 ns" { clk clk~combout clk_temp1 clk_temp1~clkctrl count[29] } { 0.000ns 0.000ns 1.934ns 1.751ns 0.936ns } { 0.000ns 0.945ns 0.206ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.438 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 6.438 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns clk 1 CLK PIN_25 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_25; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.934 ns) + CELL(0.206 ns) 3.085 ns clk_temp1 2 COMB LCCOMB_X15_Y10_N0 1 " "Info: 2: + IC(1.934 ns) + CELL(0.206 ns) = 3.085 ns; Loc. = LCCOMB_X15_Y10_N0; Fanout = 1; COMB Node = 'clk_temp1'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.140 ns" { clk clk_temp1 } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.751 ns) + CELL(0.000 ns) 4.836 ns clk_temp1~clkctrl 3 COMB CLKCTRL_G4 33 " "Info: 3: + IC(1.751 ns) + CELL(0.000 ns) = 4.836 ns; Loc. = CLKCTRL_G4; Fanout = 33; COMB Node = 'clk_temp1~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.751 ns" { clk_temp1 clk_temp1~clkctrl } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.936 ns) + CELL(0.666 ns) 6.438 ns count\[1\] 4 REG LCFF_X13_Y18_N19 3 " "Info: 4: + IC(0.936 ns) + CELL(0.666 ns) = 6.438 ns; Loc. = LCFF_X13_Y18_N19; Fanout = 3; REG Node = 'count\[1\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.602 ns" { clk_temp1~clkctrl count[1] } "NODE_NAME" } } { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.817 ns ( 28.22 % ) " "Info: Total cell delay = 1.817 ns ( 28.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.621 ns ( 71.78 % ) " "Info: Total interconnect delay = 4.621 ns ( 71.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.438 ns" { clk clk_temp1 clk_temp1~clkctrl count[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.438 ns" { clk clk~combout clk_temp1 clk_temp1~clkctrl count[1] } { 0.000ns 0.000ns 1.934ns 1.751ns 0.936ns } { 0.000ns 0.945ns 0.206ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.438 ns" { clk clk_temp1 clk_temp1~clkctrl count[29] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.438 ns" { clk clk~combout clk_temp1 clk_temp1~clkctrl count[29] } { 0.000ns 0.000ns 1.934ns 1.751ns 0.936ns } { 0.000ns 0.945ns 0.206ns 0.000ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.438 ns" { clk clk_temp1 clk_temp1~clkctrl count[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.438 ns" { clk clk~combout clk_temp1 clk_temp1~clkctrl count[1] } { 0.000ns 0.000ns 1.934ns 1.751ns 0.936ns } { 0.000ns 0.945ns 0.206ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "div_half.vhd" "" { Text "D:/my_eda/div_half/div_half.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.115 ns" { count[1] Add0~419 Add0~421 Add0~423 Add0~425 Add0~427 Add0~429 Add0~431 Add0~433 Add0~435 Add0~437 Add0~439 Add0~441 Add0~443 Add0~445 Add0~447 Add0~449 Add0~451 Add0~453 Add0~455 Add0~457 Add0~459 Add0~461 Add0~463 Add0~465 Add0~467 Add0~469 Add0~471 Add0~473 Add0~474 count~436 count[29] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.115 ns" { count[1] Add0~419 Add0~421 Add0~423 Add0~425 Add0~427 Add0~429 Add0~431 Add0~433 Add0~435 Add0~437 Add0~439 Add0~441 Add0~443 Add0~445 Add0~447 Add0~449 Add0~451 Add0~453 Add0~455 Add0~457 Add0~459 Add0~461 Add0~463 Add0~465 Add0~467 Add0~469 Add0~471 Add0~473 Add0~474 count~436 count[29] } { 0.000ns 0.755ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.325ns 0.000ns } { 0.000ns 0.596ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.206ns 0.108ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.438 ns" { clk clk_temp1 clk_temp1~clkctrl count[29] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.438 ns" { clk clk~combout clk_temp1 clk_temp1~clkctrl count[29] } { 0.000ns 0.000ns 1.934ns 1.751ns 0.936ns } { 0.000ns 0.945ns 0.206ns 0.000ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.438 ns" { clk clk_temp1 clk_temp1~clkctrl count[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.438 ns" { clk clk~combout clk_temp1 clk_temp1~clkctrl count[1] } { 0.000ns 0.000ns 1.934ns 1.751ns 0.936ns } { 0.000ns 0.945ns 0.206ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
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