div5.tan.rpt

大量VHDL写的数字系统设计有用实例达到

; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt1[0]   ; cnt1[2]   ; clk        ; clk      ; None                        ; None                      ; 1.234 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt2[2]   ; clk_temp2 ; clk        ; clk      ; None                        ; None                      ; 1.226 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt2[1]   ; clk_temp2 ; clk        ; clk      ; None                        ; None                      ; 1.199 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt2[1]   ; cnt2[2]   ; clk        ; clk      ; None                        ; None                      ; 1.194 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt2[2]   ; cnt2[0]   ; clk        ; clk      ; None                        ; None                      ; 1.181 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt1[2]   ; clk_temp1 ; clk        ; clk      ; None                        ; None                      ; 1.171 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt1[2]   ; cnt1[0]   ; clk        ; clk      ; None                        ; None                      ; 1.125 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt2[0]   ; cnt2[1]   ; clk        ; clk      ; None                        ; None                      ; 1.061 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt2[0]   ; clk_temp2 ; clk        ; clk      ; None                        ; None                      ; 1.059 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt2[0]   ; cnt2[2]   ; clk        ; clk      ; None                        ; None                      ; 1.056 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt1[1]   ; cnt1[0]   ; clk        ; clk      ; None                        ; None                      ; 0.775 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt2[1]   ; cnt2[0]   ; clk        ; clk      ; None                        ; None                      ; 0.773 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt1[1]   ; cnt1[2]   ; clk        ; clk      ; None                        ; None                      ; 0.772 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt1[1]   ; clk_temp1 ; clk        ; clk      ; None                        ; None                      ; 0.770 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt1[0]   ; cnt1[1]   ; clk        ; clk      ; None                        ; None                      ; 0.757 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; clk_temp2 ; clk_temp2 ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt2[2]   ; cnt2[2]   ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt2[1]   ; cnt2[1]   ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt2[0]   ; cnt2[0]   ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; clk_temp1 ; clk_temp1 ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt1[0]   ; cnt1[0]   ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt1[2]   ; cnt1[2]   ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt1[1]   ; cnt1[1]   ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
+-------+------------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+-----------+------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To   ; From Clock ;
+-------+--------------+------------+-----------+------+------------+
; N/A   ; None         ; 8.174 ns   ; clk_temp2 ; div5 ; clk        ;
; N/A   ; None         ; 7.689 ns   ; clk_temp1 ; div5 ; clk        ;
+-------+--------------+------------+-----------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Tue Mar 27 16:12:55 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off div5 -c div5 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 340.02 MHz between source register "cnt1[0]" and destination register "clk_temp1"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.235 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y5_N11; Fanout = 4; REG Node = 'cnt1[0]'
            Info: 2: + IC(0.476 ns) + CELL(0.651 ns) = 1.127 ns; Loc. = LCCOMB_X33_Y5_N24; Fanout = 1; COMB Node = 'clk_temp1~68'
            Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.235 ns; Loc. = LCFF_X33_Y5_N25; Fanout = 2; REG Node = 'clk_temp1'
            Info: Total cell delay = 0.759 ns ( 61.46 % )
            Info: Total interconnect delay = 0.476 ns ( 38.54 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.817 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.922 ns) + CELL(0.666 ns) = 2.817 ns; Loc. = LCFF_X33_Y5_N25; Fanout = 2; REG Node = 'clk_temp1'
                Info: Total cell delay = 1.756 ns ( 62.34 % )
                Info: Total interconnect delay = 1.061 ns ( 37.66 % )
            Info: - Longest clock path from clock "clk" to source register is 2.817 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.922 ns) + CELL(0.666 ns) = 2.817 ns; Loc. = LCFF_X33_Y5_N11; Fanout = 4; REG Node = 'cnt1[0]'
                Info: Total cell delay = 1.756 ns ( 62.34 % )
                Info: Total interconnect delay = 1.061 ns ( 37.66 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tco from clock "clk" to destination pin "div5" through register "clk_temp2" is 8.174 ns
    Info: + Longest clock path from clock "clk" to source register is 2.817 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.922 ns) + CELL(0.666 ns) = 2.817 ns; Loc. = LCFF_X33_Y5_N5; Fanout = 2; REG Node = 'clk_temp2'
        Info: Total cell delay = 1.756 ns ( 62.34 % )
        Info: Total interconnect delay = 1.061 ns ( 37.66 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 5.053 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y5_N5; Fanout = 2; REG Node = 'clk_temp2'
        Info: 2: + IC(0.763 ns) + CELL(0.651 ns) = 1.414 ns; Loc. = LCCOMB_X33_Y5_N14; Fanout = 1; COMB Node = 'div5~0'
        Info: 3: + IC(0.593 ns) + CELL(3.046 ns) = 5.053 ns; Loc. = PIN_79; Fanout = 0; PIN Node = 'div5'
        Info: Total cell delay = 3.697 ns ( 73.16 % )
        Info: Total interconnect delay = 1.356 ns ( 26.84 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Mar 27 16:12:56 2007
    Info: Elapsed time: 00:00:02