cnt24_1.tan.rpt

大量VHDL写的数字系统设计有用实例达到

; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; 74160:inst1|6 ; 74160:inst|9  ; clk        ; clk      ; None                        ; None                      ; 1.509 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; 74160:inst|7  ; 74160:inst|9  ; clk        ; clk      ; None                        ; None                      ; 1.486 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; 74160:inst1|6 ; 74160:inst1|9 ; clk        ; clk      ; None                        ; None                      ; 1.485 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; 74160:inst1|9 ; 74160:inst|8  ; clk        ; clk      ; None                        ; None                      ; 1.357 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; 74160:inst1|9 ; 74160:inst|7  ; clk        ; clk      ; None                        ; None                      ; 1.356 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; 74160:inst1|9 ; 74160:inst|9  ; clk        ; clk      ; None                        ; None                      ; 1.353 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; 74160:inst1|9 ; 74160:inst1|7 ; clk        ; clk      ; None                        ; None                      ; 1.248 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; 74160:inst1|9 ; 74160:inst|6  ; clk        ; clk      ; None                        ; None                      ; 1.244 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; 74160:inst|7  ; 74160:inst|8  ; clk        ; clk      ; None                        ; None                      ; 1.236 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; 74160:inst1|7 ; 74160:inst1|8 ; clk        ; clk      ; None                        ; None                      ; 1.227 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; 74160:inst|9  ; 74160:inst|7  ; clk        ; clk      ; None                        ; None                      ; 1.170 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; 74160:inst1|6 ; 74160:inst|6  ; clk        ; clk      ; None                        ; None                      ; 1.094 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; 74160:inst1|6 ; 74160:inst1|8 ; clk        ; clk      ; None                        ; None                      ; 1.090 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; 74160:inst1|6 ; 74160:inst1|7 ; clk        ; clk      ; None                        ; None                      ; 1.090 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; 74160:inst1|7 ; 74160:inst1|9 ; clk        ; clk      ; None                        ; None                      ; 1.060 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; 74160:inst1|9 ; 74160:inst1|9 ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; 74160:inst1|8 ; 74160:inst1|8 ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; 74160:inst1|6 ; 74160:inst1|6 ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; 74160:inst1|7 ; 74160:inst1|7 ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; 74160:inst|7  ; 74160:inst|7  ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; 74160:inst|9  ; 74160:inst|9  ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; 74160:inst|6  ; 74160:inst|6  ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; 74160:inst|8  ; 74160:inst|8  ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+---------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From          ; To     ; From Clock ;
+-------+--------------+------------+---------------+--------+------------+
; N/A   ; None         ; 8.980 ns   ; 74160:inst1|9 ; one[3] ; clk        ;
; N/A   ; None         ; 7.655 ns   ; 74160:inst1|8 ; one[2] ; clk        ;
; N/A   ; None         ; 7.335 ns   ; 74160:inst1|7 ; one[1] ; clk        ;
; N/A   ; None         ; 7.322 ns   ; 74160:inst|6  ; ten[0] ; clk        ;
; N/A   ; None         ; 7.308 ns   ; 74160:inst|9  ; ten[3] ; clk        ;
; N/A   ; None         ; 7.074 ns   ; 74160:inst1|6 ; one[0] ; clk        ;
; N/A   ; None         ; 7.053 ns   ; 74160:inst|8  ; ten[2] ; clk        ;
; N/A   ; None         ; 6.900 ns   ; 74160:inst|7  ; ten[1] ; clk        ;
+-------+--------------+------------+---------------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Mon Mar 12 16:26:51 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cnt24_1 -c cnt24_1 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 340.02 MHz between source register "74160:inst|6" and destination register "74160:inst|8"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.723 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y2_N9; Fanout = 3; REG Node = '74160:inst|6'
            Info: 2: + IC(0.439 ns) + CELL(0.589 ns) = 1.028 ns; Loc. = LCCOMB_X1_Y2_N22; Fanout = 3; COMB Node = '74160:inst|50~10'
            Info: 3: + IC(0.381 ns) + CELL(0.206 ns) = 1.615 ns; Loc. = LCCOMB_X1_Y2_N4; Fanout = 1; COMB Node = '74160:inst|8~25'
            Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 1.723 ns; Loc. = LCFF_X1_Y2_N5; Fanout = 3; REG Node = '74160:inst|8'
            Info: Total cell delay = 0.903 ns ( 52.41 % )
            Info: Total interconnect delay = 0.820 ns ( 47.59 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.816 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.816 ns; Loc. = LCFF_X1_Y2_N5; Fanout = 3; REG Node = '74160:inst|8'
                Info: Total cell delay = 1.756 ns ( 62.36 % )
                Info: Total interconnect delay = 1.060 ns ( 37.64 % )
            Info: - Longest clock path from clock "clk" to source register is 2.816 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.816 ns; Loc. = LCFF_X1_Y2_N9; Fanout = 3; REG Node = '74160:inst|6'
                Info: Total cell delay = 1.756 ns ( 62.36 % )
                Info: Total interconnect delay = 1.060 ns ( 37.64 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tco from clock "clk" to destination pin "one[3]" through register "74160:inst1|9" is 8.980 ns
    Info: + Longest clock path from clock "clk" to source register is 2.816 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.816 ns; Loc. = LCFF_X1_Y2_N7; Fanout = 5; REG Node = '74160:inst1|9'
        Info: Total cell delay = 1.756 ns ( 62.36 % )
        Info: Total interconnect delay = 1.060 ns ( 37.64 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 5.860 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y2_N7; Fanout = 5; REG Node = '74160:inst1|9'
        Info: 2: + IC(2.794 ns) + CELL(3.066 ns) = 5.860 ns; Loc. = PIN_74; Fanout = 0; PIN Node = 'one[3]'
        Info: Total cell delay = 3.066 ns ( 52.32 % )
        Info: Total interconnect delay = 2.794 ns ( 47.68 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Mar 12 16:26:52 2007
    Info: Elapsed time: 00:00:02