cnt24_1.tan.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register 74160:inst\|6 74160:inst\|8 340.02 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 340.02 MHz between source register \"74160:inst\|6\" and destination register \"74160:inst\|8\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.941 ns " "Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.723 ns + Longest register register " "Info: + Longest register to register delay is 1.723 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 74160:inst\|6 1 REG LCFF_X1_Y2_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y2_N9; Fanout = 3; REG Node = '74160:inst\|6'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { 74160:inst|6 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/altera60/quartus60/libraries/others/maxplus2/74160.bdf" { { 64 1032 1096 144 "6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.439 ns) + CELL(0.589 ns) 1.028 ns 74160:inst\|50~10 2 COMB LCCOMB_X1_Y2_N22 3 " "Info: 2: + IC(0.439 ns) + CELL(0.589 ns) = 1.028 ns; Loc. = LCCOMB_X1_Y2_N22; Fanout = 3; COMB Node = '74160:inst\|50~10'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.028 ns" { 74160:inst|6 74160:inst|50~10 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/altera60/quartus60/libraries/others/maxplus2/74160.bdf" { { 376 680 744 416 "50" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.381 ns) + CELL(0.206 ns) 1.615 ns 74160:inst\|8~25 3 COMB LCCOMB_X1_Y2_N4 1 " "Info: 3: + IC(0.381 ns) + CELL(0.206 ns) = 1.615 ns; Loc. = LCCOMB_X1_Y2_N4; Fanout = 1; COMB Node = '74160:inst\|8~25'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.587 ns" { 74160:inst|50~10 74160:inst|8~25 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/altera60/quartus60/libraries/others/maxplus2/74160.bdf" { { 544 1032 1096 624 "8" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.723 ns 74160:inst\|8 4 REG LCFF_X1_Y2_N5 3 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 1.723 ns; Loc. = LCFF_X1_Y2_N5; Fanout = 3; REG Node = '74160:inst\|8'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { 74160:inst|8~25 74160:inst|8 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/altera60/quartus60/libraries/others/maxplus2/74160.bdf" { { 544 1032 1096 624 "8" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.903 ns ( 52.41 % ) " "Info: Total cell delay = 0.903 ns ( 52.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.820 ns ( 47.59 % ) " "Info: Total interconnect delay = 0.820 ns ( 47.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.723 ns" { 74160:inst|6 74160:inst|50~10 74160:inst|8~25 74160:inst|8 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "1.723 ns" { 74160:inst|6 74160:inst|50~10 74160:inst|8~25 74160:inst|8 } { 0.000ns 0.439ns 0.381ns 0.000ns } { 0.000ns 0.589ns 0.206ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.816 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.816 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cnt24_1.bdf" "" { Schematic "D:/my_eda/cnt24_1/cnt24_1.bdf" { { 120 8 176 136 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "cnt24_1.bdf" "" { Schematic "D:/my_eda/cnt24_1/cnt24_1.bdf" { { 120 8 176 136 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.921 ns) + CELL(0.666 ns) 2.816 ns 74160:inst\|8 3 REG LCFF_X1_Y2_N5 3 " "Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.816 ns; Loc. = LCFF_X1_Y2_N5; Fanout = 3; REG Node = '74160:inst\|8'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.587 ns" { clk~clkctrl 74160:inst|8 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/altera60/quartus60/libraries/others/maxplus2/74160.bdf" { { 544 1032 1096 624 "8" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.36 % ) " "Info: Total cell delay = 1.756 ns ( 62.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.060 ns ( 37.64 % ) " "Info: Total interconnect delay = 1.060 ns ( 37.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.816 ns" { clk clk~clkctrl 74160:inst|8 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.816 ns" { clk clk~combout clk~clkctrl 74160:inst|8 } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.816 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.816 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cnt24_1.bdf" "" { Schematic "D:/my_eda/cnt24_1/cnt24_1.bdf" { { 120 8 176 136 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "cnt24_1.bdf" "" { Schematic "D:/my_eda/cnt24_1/cnt24_1.bdf" { { 120 8 176 136 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.921 ns) + CELL(0.666 ns) 2.816 ns 74160:inst\|6 3 REG LCFF_X1_Y2_N9 3 " "Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.816 ns; Loc. = LCFF_X1_Y2_N9; Fanout = 3; REG Node = '74160:inst\|6'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.587 ns" { clk~clkctrl 74160:inst|6 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/altera60/quartus60/libraries/others/maxplus2/74160.bdf" { { 64 1032 1096 144 "6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.36 % ) " "Info: Total cell delay = 1.756 ns ( 62.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.060 ns ( 37.64 % ) " "Info: Total interconnect delay = 1.060 ns ( 37.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.816 ns" { clk clk~clkctrl 74160:inst|6 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.816 ns" { clk clk~combout clk~clkctrl 74160:inst|6 } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.816 ns" { clk clk~clkctrl 74160:inst|8 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.816 ns" { clk clk~combout clk~clkctrl 74160:inst|8 } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.816 ns" { clk clk~clkctrl 74160:inst|6 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.816 ns" { clk clk~combout clk~clkctrl 74160:inst|6 } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "74160.bdf" "" { Schematic "e:/altera60/quartus60/libraries/others/maxplus2/74160.bdf" { { 64 1032 1096 144 "6" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "74160.bdf" "" { Schematic "e:/altera60/quartus60/libraries/others/maxplus2/74160.bdf" { { 544 1032 1096 624 "8" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.723 ns" { 74160:inst|6 74160:inst|50~10 74160:inst|8~25 74160:inst|8 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "1.723 ns" { 74160:inst|6 74160:inst|50~10 74160:inst|8~25 74160:inst|8 } { 0.000ns 0.439ns 0.381ns 0.000ns } { 0.000ns 0.589ns 0.206ns 0.108ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.816 ns" { clk clk~clkctrl 74160:inst|8 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.816 ns" { clk clk~combout clk~clkctrl 74160:inst|8 } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.816 ns" { clk clk~clkctrl 74160:inst|6 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.816 ns" { clk clk~combout clk~clkctrl 74160:inst|6 } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { 74160:inst|8 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { 74160:inst|8 } {  } {  } } } { "74160.bdf" "" { Schematic "e:/altera60/quartus60/libraries/others/maxplus2/74160.bdf" { { 544 1032 1096 624 "8" "" } } } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk one\[3\] 74160:inst1\|9 8.980 ns register " "Info: tco from clock \"clk\" to destination pin \"one\[3\]\" through register \"74160:inst1\|9\" is 8.980 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.816 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.816 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cnt24_1.bdf" "" { Schematic "D:/my_eda/cnt24_1/cnt24_1.bdf" { { 120 8 176 136 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "cnt24_1.bdf" "" { Schematic "D:/my_eda/cnt24_1/cnt24_1.bdf" { { 120 8 176 136 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.921 ns) + CELL(0.666 ns) 2.816 ns 74160:inst1\|9 3 REG LCFF_X1_Y2_N7 5 " "Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.816 ns; Loc. = LCFF_X1_Y2_N7; Fanout = 5; REG Node = '74160:inst1\|9'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.587 ns" { clk~clkctrl 74160:inst1|9 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/altera60/quartus60/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.36 % ) " "Info: Total cell delay = 1.756 ns ( 62.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.060 ns ( 37.64 % ) " "Info: Total interconnect delay = 1.060 ns ( 37.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.816 ns" { clk clk~clkctrl 74160:inst1|9 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.816 ns" { clk clk~combout clk~clkctrl 74160:inst1|9 } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "74160.bdf" "" { Schematic "e:/altera60/quartus60/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.860 ns + Longest register pin " "Info: + Longest register to pin delay is 5.860 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 74160:inst1\|9 1 REG LCFF_X1_Y2_N7 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y2_N7; Fanout = 5; REG Node = '74160:inst1\|9'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { 74160:inst1|9 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/altera60/quartus60/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.794 ns) + CELL(3.066 ns) 5.860 ns one\[3\] 2 PIN PIN_74 0 " "Info: 2: + IC(2.794 ns) + CELL(3.066 ns) = 5.860 ns; Loc. = PIN_74; Fanout = 0; PIN Node = 'one\[3\]'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "5.860 ns" { 74160:inst1|9 one[3] } "NODE_NAME" } } { "cnt24_1.bdf" "" { Schematic "D:/my_eda/cnt24_1/cnt24_1.bdf" { { 368 576 592 544 "one\[0\]" "" } { 368 560 576 544 "one\[1\]" "" } { 368 544 560 544 "one\[2\]" "" } { 368 528 544 544 "one\[3\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.066 ns ( 52.32 % ) " "Info: Total cell delay = 3.066 ns ( 52.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.794 ns ( 47.68 % ) " "Info: Total interconnect delay = 2.794 ns ( 47.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "5.860 ns" { 74160:inst1|9 one[3] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "5.860 ns" { 74160:inst1|9 one[3] } { 0.000ns 2.794ns } { 0.000ns 3.066ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.816 ns" { clk clk~clkctrl 74160:inst1|9 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.816 ns" { clk clk~combout clk~clkctrl 74160:inst1|9 } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "5.860 ns" { 74160:inst1|9 one[3] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "5.860 ns" { 74160:inst1|9 one[3] } { 0.000ns 2.794ns } { 0.000ns 3.066ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 12 16:26:52 2007 " "Info: Processing ended: Mon Mar 12 16:26:52 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}