cnt24_1.map.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 12 16:26:28 2007 " "Info: Processing started: Mon Mar 12 16:26:28 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off cnt24_1 -c cnt24_1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cnt24_1 -c cnt24_1" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt24_1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file cnt24_1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 cnt24_1 " "Info: Found entity 1: cnt24_1" {  } { { "cnt24_1.bdf" "" { Schematic "D:/my_eda/cnt24_1/cnt24_1.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "cnt24_1 " "Info: Elaborating entity \"cnt24_1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera60/quartus60/libraries/others/maxplus2/74160.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera60/quartus60/libraries/others/maxplus2/74160.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74160 " "Info: Found entity 1: 74160" {  } { { "74160.bdf" "" { Schematic "e:/altera60/quartus60/libraries/others/maxplus2/74160.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74160 74160:inst1 " "Info: Elaborating entity \"74160\" for hierarchy \"74160:inst1\"" {  } { { "cnt24_1.bdf" "inst1" { Schematic "D:/my_eda/cnt24_1/cnt24_1.bdf" { { 184 456 640 304 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "74160:inst1 " "Info: Elaborated megafunction instantiation \"74160:inst1\"" {  } { { "cnt24_1.bdf" "" { Schematic "D:/my_eda/cnt24_1/cnt24_1.bdf" { { 184 456 640 304 "inst1" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "19 " "Info: Implemented 19 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "10 " "Info: Implemented 10 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 12 16:26:30 2007 " "Info: Processing ended: Mon Mar 12 16:26:30 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}