📄 yb_cnt16.tan.rpt
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Timing Analyzer report for yb_cnt16
Mon Mar 12 22:02:10 2007
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
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; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tco
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------------+-------------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------------+-------------------------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 11.313 ns ; yb_dff:\l1:3:yb_dffx|qn ; q[3] ; clk ; -- ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 360.10 MHz ( period = 2.777 ns ) ; yb_dff:\l1:3:yb_dffx|qn ; yb_dff:\l1:3:yb_dffx|qn ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------------+-------------------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C8T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+-------------------------+-------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------------------------+-------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 360.10 MHz ( period = 2.777 ns ) ; yb_dff:\l1:0:yb_dffx|qn ; yb_dff:\l1:0:yb_dffx|qn ; clk ; clk ; None ; None ; 0.501 ns ;
; N/A ; Restricted to 360.10 MHz ( period = 2.777 ns ) ; yb_dff:\l1:1:yb_dffx|qn ; yb_dff:\l1:1:yb_dffx|qn ; clk ; clk ; None ; None ; 0.501 ns ;
; N/A ; Restricted to 360.10 MHz ( period = 2.777 ns ) ; yb_dff:\l1:2:yb_dffx|qn ; yb_dff:\l1:2:yb_dffx|qn ; clk ; clk ; None ; None ; 0.501 ns ;
; N/A ; Restricted to 360.10 MHz ( period = 2.777 ns ) ; yb_dff:\l1:3:yb_dffx|qn ; yb_dff:\l1:3:yb_dffx|qn ; clk ; clk ; None ; None ; 0.501 ns ;
+-------+------------------------------------------------+-------------------------+-------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+---------------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-------------------------+------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-------------------------+------+------------+
; N/A ; None ; 11.313 ns ; yb_dff:\l1:3:yb_dffx|qn ; q[3] ; clk ;
; N/A ; None ; 9.962 ns ; yb_dff:\l1:2:yb_dffx|qn ; q[2] ; clk ;
; N/A ; None ; 8.154 ns ; yb_dff:\l1:1:yb_dffx|qn ; q[1] ; clk ;
; N/A ; None ; 7.359 ns ; yb_dff:\l1:0:yb_dffx|qn ; q[0] ; clk ;
+-------+--------------+------------+-------------------------+------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
Info: Processing started: Mon Mar 12 22:02:09 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off yb_cnt16 -c yb_cnt16 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected ripple clock "yb_dff:\l1:2:yb_dffx|qn" as buffer
Info: Detected ripple clock "yb_dff:\l1:1:yb_dffx|qn" as buffer
Info: Detected ripple clock "yb_dff:\l1:0:yb_dffx|qn" as buffer
Info: Clock "clk" Internal fmax is restricted to 360.1 MHz between source register "yb_dff:\l1:0:yb_dffx|qn" and destination register "yb_dff:\l1:0:yb_dffx|qn"
Info: fmax restricted to clock pin edge rate 2.777 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 0.501 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y2_N3; Fanout = 3; REG Node = 'yb_dff:\l1:0:yb_dffx|qn'
Info: 2: + IC(0.000 ns) + CELL(0.393 ns) = 0.393 ns; Loc. = LCCOMB_X1_Y2_N2; Fanout = 1; COMB Node = 'yb_dff:\l1:0:yb_dffx|qn~2'
Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.501 ns; Loc. = LCFF_X1_Y2_N3; Fanout = 3; REG Node = 'yb_dff:\l1:0:yb_dffx|qn'
Info: Total cell delay = 0.501 ns ( 100.00 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 2.530 ns
Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_30; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.919 ns) + CELL(0.666 ns) = 2.530 ns; Loc. = LCFF_X1_Y2_N3; Fanout = 3; REG Node = 'yb_dff:\l1:0:yb_dffx|qn'
Info: Total cell delay = 1.611 ns ( 63.68 % )
Info: Total interconnect delay = 0.919 ns ( 36.32 % )
Info: - Longest clock path from clock "clk" to source register is 2.530 ns
Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_30; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.919 ns) + CELL(0.666 ns) = 2.530 ns; Loc. = LCFF_X1_Y2_N3; Fanout = 3; REG Node = 'yb_dff:\l1:0:yb_dffx|qn'
Info: Total cell delay = 1.611 ns ( 63.68 % )
Info: Total interconnect delay = 0.919 ns ( 36.32 % )
Info: + Micro clock to output delay of source is 0.304 ns
Info: + Micro setup delay of destination is -0.040 ns
Info: tco from clock "clk" to destination pin "q[3]" through register "yb_dff:\l1:3:yb_dffx|qn" is 11.313 ns
Info: + Longest clock path from clock "clk" to source register is 6.835 ns
Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_30; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.919 ns) + CELL(0.970 ns) = 2.834 ns; Loc. = LCFF_X1_Y2_N3; Fanout = 3; REG Node = 'yb_dff:\l1:0:yb_dffx|qn'
Info: 3: + IC(0.396 ns) + CELL(0.970 ns) = 4.200 ns; Loc. = LCFF_X1_Y2_N15; Fanout = 3; REG Node = 'yb_dff:\l1:1:yb_dffx|qn'
Info: 4: + IC(0.606 ns) + CELL(0.970 ns) = 5.776 ns; Loc. = LCFF_X2_Y2_N9; Fanout = 3; REG Node = 'yb_dff:\l1:2:yb_dffx|qn'
Info: 5: + IC(0.393 ns) + CELL(0.666 ns) = 6.835 ns; Loc. = LCFF_X2_Y2_N21; Fanout = 2; REG Node = 'yb_dff:\l1:3:yb_dffx|qn'
Info: Total cell delay = 4.521 ns ( 66.14 % )
Info: Total interconnect delay = 2.314 ns ( 33.86 % )
Info: + Micro clock to output delay of source is 0.304 ns
Info: + Longest register to pin delay is 4.174 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y2_N21; Fanout = 2; REG Node = 'yb_dff:\l1:3:yb_dffx|qn'
Info: 2: + IC(0.938 ns) + CELL(3.236 ns) = 4.174 ns; Loc. = PIN_43; Fanout = 0; PIN Node = 'q[3]'
Info: Total cell delay = 3.236 ns ( 77.53 % )
Info: Total interconnect delay = 0.938 ns ( 22.47 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
Info: Processing ended: Mon Mar 12 22:02:10 2007
Info: Elapsed time: 00:00:02
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