yb_cnt16.vhd

大量VHDL写的数字系统设计有用实例达到

library ieee;
use ieee.std_logic_1164.all;
entity yb_dff is
port(clk:in std_logic;
     rst:in std_logic;
     d:in std_logic;
     q:out std_logic;
     qn:out std_logic);
end;
architecture one of yb_dff is
begin
process(clk,rst)
begin
if rst='0' then q<='0';qn<='1';
elsif clk'event and clk='1' then
q<=d;
qn<=not d;
end if ;
end process;
end;
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library ieee;
use ieee.std_logic_1164.all;
entity yb_cnt16 is
port(clk:in std_logic;
     rst:in std_logic;
     q:out std_logic_vector(3 downto 0));
     
end;
architecture one of yb_cnt16 is
	component yb_dff
	port(clk:in std_logic;
     rst:in std_logic;
     d:in std_logic;
     q:out std_logic;
     qn:out std_logic);
	end component;
signal q_temp:std_logic_vector(4 downto 0);
begin
q_temp(0)<=clk;
l1:for i in 0 to 3 generate
yb_dffx:yb_dff 
 port map (q_temp(i),rst,q_temp(i+1),q(i),q_temp(i+1));
end generate l1;
end;