bcd_decoder.vho

大量VHDL写的数字系统设计有用实例达到

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version"

-- DATE "03/03/2007 20:51:37"

-- 
-- Device: Altera EP2C8T144C8 Package TQFP144
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, cycloneii;
USE IEEE.std_logic_1164.all;
USE cycloneii.cycloneii_components.all;

ENTITY 	bcd_decoder IS
    PORT (
	i0 : IN std_logic;
	i1 : IN std_logic;
	i2 : IN std_logic;
	i3 : IN std_logic;
	y0 : OUT std_logic;
	y1 : OUT std_logic;
	y2 : OUT std_logic;
	y3 : OUT std_logic;
	y4 : OUT std_logic;
	y5 : OUT std_logic;
	y6 : OUT std_logic
	);
END bcd_decoder;

ARCHITECTURE structure OF bcd_decoder IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '0';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_i0: std_logic;
SIGNAL ww_i1: std_logic;
SIGNAL ww_i2: std_logic;
SIGNAL ww_i3: std_logic;
SIGNAL ww_y0: std_logic;
SIGNAL ww_y1: std_logic;
SIGNAL ww_y2: std_logic;
SIGNAL ww_y3: std_logic;
SIGNAL ww_y4: std_logic;
SIGNAL ww_y5: std_logic;
SIGNAL ww_y6: std_logic;
SIGNAL \i[1]~combout\ : std_logic;
SIGNAL \i[2]~combout\ : std_logic;
SIGNAL \i[3]~combout\ : std_logic;
SIGNAL \i[0]~combout\ : std_logic;
SIGNAL \Mux6~3\ : std_logic;
SIGNAL \Mux5~3\ : std_logic;
SIGNAL \Mux4~3\ : std_logic;
SIGNAL \Mux3~3\ : std_logic;
SIGNAL \Mux2~3\ : std_logic;
SIGNAL \Mux1~3\ : std_logic;
SIGNAL \Mux0~3\ : std_logic;
SIGNAL \ALT_INV_Mux6~3\ : std_logic;
SIGNAL \ALT_INV_Mux5~3\ : std_logic;
SIGNAL \ALT_INV_Mux4~3\ : std_logic;
SIGNAL \ALT_INV_Mux3~3\ : std_logic;
SIGNAL \ALT_INV_Mux2~3\ : std_logic;
SIGNAL \ALT_INV_Mux1~3\ : std_logic;

BEGIN

ww_i0 <= i0;
ww_i1 <= i1;
ww_i2 <= i2;
ww_i3 <= i3;
y0 <= ww_y0;
y1 <= ww_y1;
y2 <= ww_y2;
y3 <= ww_y3;
y4 <= ww_y4;
y5 <= ww_y5;
y6 <= ww_y6;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
\ALT_INV_Mux6~3\ <= NOT \Mux6~3\;
\ALT_INV_Mux5~3\ <= NOT \Mux5~3\;
\ALT_INV_Mux4~3\ <= NOT \Mux4~3\;
\ALT_INV_Mux3~3\ <= NOT \Mux3~3\;
\ALT_INV_Mux2~3\ <= NOT \Mux2~3\;
\ALT_INV_Mux1~3\ <= NOT \Mux1~3\;

\i[1]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_i1,
	combout => \i[1]~combout\);

\i[2]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_i2,
	combout => \i[2]~combout\);

\i[3]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_i3,
	combout => \i[3]~combout\);

\i[0]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_i0,
	combout => \i[0]~combout\);

\Mux6~3_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Mux6~3\ = \i[2]~combout\ & !\i[1]~combout\ & (\i[3]~combout\ $ !\i[0]~combout\) # !\i[2]~combout\ & \i[0]~combout\ & (\i[1]~combout\ $ !\i[3]~combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0110000100000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \i[1]~combout\,
	datab => \i[2]~combout\,
	datac => \i[3]~combout\,
	datad => \i[0]~combout\,
	combout => \Mux6~3\);

\Mux5~3_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Mux5~3\ = \i[1]~combout\ & (\i[0]~combout\ & (\i[3]~combout\) # !\i[0]~combout\ & \i[2]~combout\) # !\i[1]~combout\ & \i[2]~combout\ & (\i[3]~combout\ $ \i[0]~combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010011001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \i[1]~combout\,
	datab => \i[2]~combout\,
	datac => \i[3]~combout\,
	datad => \i[0]~combout\,
	combout => \Mux5~3\);

\Mux4~3_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Mux4~3\ = \i[2]~combout\ & \i[3]~combout\ & (\i[1]~combout\ # !\i[0]~combout\) # !\i[2]~combout\ & \i[1]~combout\ & !\i[3]~combout\ & !\i[0]~combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000011000010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \i[1]~combout\,
	datab => \i[2]~combout\,
	datac => \i[3]~combout\,
	datad => \i[0]~combout\,
	combout => \Mux4~3\);

\Mux3~3_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Mux3~3\ = \i[1]~combout\ & (\i[2]~combout\ & (\i[0]~combout\) # !\i[2]~combout\ & \i[3]~combout\ & !\i[0]~combout\) # !\i[1]~combout\ & !\i[3]~combout\ & (\i[2]~combout\ $ \i[0]~combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000100100100100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \i[1]~combout\,
	datab => \i[2]~combout\,
	datac => \i[3]~combout\,
	datad => \i[0]~combout\,
	combout => \Mux3~3\);

\Mux2~3_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Mux2~3\ = \i[1]~combout\ & (!\i[3]~combout\ & \i[0]~combout\) # !\i[1]~combout\ & (\i[2]~combout\ & !\i[3]~combout\ # !\i[2]~combout\ & (\i[0]~combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0001111100000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \i[1]~combout\,
	datab => \i[2]~combout\,
	datac => \i[3]~combout\,
	datad => \i[0]~combout\,
	combout => \Mux2~3\);

\Mux1~3_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Mux1~3\ = \i[1]~combout\ & !\i[2]~combout\ & !\i[3]~combout\ # !\i[1]~combout\ & \i[0]~combout\ & (\i[2]~combout\ $ !\i[3]~combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100001100000010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \i[1]~combout\,
	datab => \i[2]~combout\,
	datac => \i[3]~combout\,
	datad => \i[0]~combout\,
	combout => \Mux1~3\);

\Mux0~3_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Mux0~3\ = \i[0]~combout\ & (\i[3]~combout\ # \i[1]~combout\ $ \i[2]~combout\) # !\i[0]~combout\ & (\i[1]~combout\ # \i[2]~combout\ $ \i[3]~combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111011010111110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \i[1]~combout\,
	datab => \i[2]~combout\,
	datac => \i[3]~combout\,
	datad => \i[0]~combout\,
	combout => \Mux0~3\);

\y[0]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \ALT_INV_Mux6~3\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_y0);

\y[1]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \ALT_INV_Mux5~3\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_y1);

\y[2]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \ALT_INV_Mux4~3\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_y2);

\y[3]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \ALT_INV_Mux3~3\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_y3);

\y[4]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \ALT_INV_Mux2~3\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_y4);

\y[5]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \ALT_INV_Mux1~3\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_y5);

\y[6]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \Mux0~3\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_y6);
END structure;