latch8.tan.rpt

大量VHDL写的数字系统设计有用实例达到

; N/A   ; None         ; 7.219 ns   ; 74373:inst|18 ; Q[6] ; G          ;
; N/A   ; None         ; 7.148 ns   ; 74373:inst|15 ; Q[3] ; G          ;
; N/A   ; None         ; 6.929 ns   ; 74373:inst|19 ; Q[7] ; G          ;
; N/A   ; None         ; 6.911 ns   ; 74373:inst|13 ; Q[1] ; G          ;
; N/A   ; None         ; 6.807 ns   ; 74373:inst|16 ; Q[4] ; G          ;
; N/A   ; None         ; 6.787 ns   ; 74373:inst|12 ; Q[0] ; G          ;
+-------+--------------+------------+---------------+------+------------+


+-----------------------------------------------------------+
; tpd                                                       ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To   ;
+-------+-------------------+-----------------+------+------+
; N/A   ; None              ; 10.372 ns       ; OE   ; Q[5] ;
; N/A   ; None              ; 10.360 ns       ; OE   ; Q[1] ;
; N/A   ; None              ; 10.002 ns       ; OE   ; Q[7] ;
; N/A   ; None              ; 9.982 ns        ; OE   ; Q[2] ;
; N/A   ; None              ; 9.982 ns        ; OE   ; Q[3] ;
; N/A   ; None              ; 9.982 ns        ; OE   ; Q[6] ;
; N/A   ; None              ; 9.569 ns        ; OE   ; Q[0] ;
; N/A   ; None              ; 9.541 ns        ; OE   ; Q[4] ;
+-------+-------------------+-----------------+------+------+


+---------------------------------------------------------------------------+
; th                                                                        ;
+---------------+-------------+-----------+------+---------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To            ; To Clock ;
+---------------+-------------+-----------+------+---------------+----------+
; N/A           ; None        ; 0.325 ns  ; D[3] ; 74373:inst|15 ; G        ;
; N/A           ; None        ; 0.006 ns  ; D[2] ; 74373:inst|14 ; G        ;
; N/A           ; None        ; -0.252 ns ; D[0] ; 74373:inst|12 ; G        ;
; N/A           ; None        ; -0.787 ns ; D[1] ; 74373:inst|13 ; G        ;
; N/A           ; None        ; -3.999 ns ; D[7] ; 74373:inst|19 ; G        ;
; N/A           ; None        ; -4.416 ns ; D[6] ; 74373:inst|18 ; G        ;
; N/A           ; None        ; -4.491 ns ; D[4] ; 74373:inst|16 ; G        ;
; N/A           ; None        ; -4.540 ns ; D[5] ; 74373:inst|17 ; G        ;
+---------------+-------------+-----------+------+---------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Fri Mar 16 16:51:04 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off latch8 -c latch8 --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "74373:inst|19" is a latch
    Warning: Node "74373:inst|18" is a latch
    Warning: Node "74373:inst|17" is a latch
    Warning: Node "74373:inst|16" is a latch
    Warning: Node "74373:inst|15" is a latch
    Warning: Node "74373:inst|14" is a latch
    Warning: Node "74373:inst|13" is a latch
    Warning: Node "74373:inst|12" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "G" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Info: tsu for register "74373:inst|17" (data pin = "D[5]", clock pin = "G") is 5.734 ns
    Info: + Longest pin to register delay is 7.366 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_59; Fanout = 1; PIN Node = 'D[5]'
        Info: 2: + IC(6.066 ns) + CELL(0.366 ns) = 7.366 ns; Loc. = LCCOMB_X22_Y1_N18; Fanout = 1; REG Node = '74373:inst|17'
        Info: Total cell delay = 1.300 ns ( 17.65 % )
        Info: Total interconnect delay = 6.066 ns ( 82.35 % )
    Info: + Micro setup delay of destination is 1.194 ns
    Info: - Shortest clock path from clock "G" to destination register is 2.826 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'G'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'G~clkctrl'
        Info: 3: + IC(1.391 ns) + CELL(0.206 ns) = 2.826 ns; Loc. = LCCOMB_X22_Y1_N18; Fanout = 1; REG Node = '74373:inst|17'
        Info: Total cell delay = 1.296 ns ( 45.86 % )
        Info: Total interconnect delay = 1.530 ns ( 54.14 % )
Info: tco from clock "G" to destination pin "Q[5]" through register "74373:inst|17" is 7.631 ns
    Info: + Longest clock path from clock "G" to source register is 2.826 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'G'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'G~clkctrl'
        Info: 3: + IC(1.391 ns) + CELL(0.206 ns) = 2.826 ns; Loc. = LCCOMB_X22_Y1_N18; Fanout = 1; REG Node = '74373:inst|17'
        Info: Total cell delay = 1.296 ns ( 45.86 % )
        Info: Total interconnect delay = 1.530 ns ( 54.14 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 4.805 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X22_Y1_N18; Fanout = 1; REG Node = '74373:inst|17'
        Info: 2: + IC(1.569 ns) + CELL(3.236 ns) = 4.805 ns; Loc. = PIN_64; Fanout = 0; PIN Node = 'Q[5]'
        Info: Total cell delay = 3.236 ns ( 67.35 % )
        Info: Total interconnect delay = 1.569 ns ( 32.65 % )
Info: Longest tpd from source pin "OE" to destination pin "Q[5]" is 10.372 ns
    Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_79; Fanout = 8; PIN Node = 'OE'
    Info: 2: + IC(6.119 ns) + CELL(3.318 ns) = 10.372 ns; Loc. = PIN_64; Fanout = 0; PIN Node = 'Q[5]'
    Info: Total cell delay = 4.253 ns ( 41.00 % )
    Info: Total interconnect delay = 6.119 ns ( 59.00 % )
Info: th for register "74373:inst|15" (data pin = "D[3]", clock pin = "G") is 0.325 ns
    Info: + Longest clock path from clock "G" to destination register is 2.789 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'G'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'G~clkctrl'
        Info: 3: + IC(1.354 ns) + CELL(0.206 ns) = 2.789 ns; Loc. = LCCOMB_X33_Y9_N18; Fanout = 1; REG Node = '74373:inst|15'
        Info: Total cell delay = 1.296 ns ( 46.47 % )
        Info: Total interconnect delay = 1.493 ns ( 53.53 % )
    Info: + Micro hold delay of destination is 0.000 ns
    Info: - Shortest pin to register delay is 2.464 ns
        Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_88; Fanout = 1; PIN Node = 'D[3]'
        Info: 2: + IC(0.988 ns) + CELL(0.366 ns) = 2.464 ns; Loc. = LCCOMB_X33_Y9_N18; Fanout = 1; REG Node = '74373:inst|15'
        Info: Total cell delay = 1.476 ns ( 59.90 % )
        Info: Total interconnect delay = 0.988 ns ( 40.10 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 10 warnings
    Info: Processing ended: Fri Mar 16 16:51:05 2007
    Info: Elapsed time: 00:00:02