latch8.map.rpt

大量VHDL写的数字系统设计有用实例达到

; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                              ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                              ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------+
; latch8.bdf                       ; yes             ; User Block Diagram/Schematic File  ; D:/my_eda/latch8/latch8.bdf                               ;
; 74373.bdf                        ; yes             ; Megafunction                       ; e:/altera60/quartus60/libraries/others/maxplus2/74373.bdf ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 8     ;
; Total combinational functions               ; 8     ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 0     ;
;     -- 3 input functions                    ; 8     ;
;     -- <=2 input functions                  ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 8     ;
;     -- arithmetic mode                      ; 0     ;
; Total registers                             ; 0     ;
; I/O pins                                    ; 18    ;
; Maximum fan-out node                        ; OE    ;
; Maximum fan-out                             ; 8     ;
; Total fan-out                               ; 40    ;
; Average fan-out                             ; 1.54  ;
+---------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                 ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
; |latch8                    ; 8 (0)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 18   ; 0            ; |latch8             ;
;    |74373:inst|            ; 8 (8)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |latch8|74373:inst  ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; 74373:inst|19                                      ; G                   ; yes                    ;
; 74373:inst|18                                      ; G                   ; yes                    ;
; 74373:inst|17                                      ; G                   ; yes                    ;
; 74373:inst|16                                      ; G                   ; yes                    ;
; 74373:inst|15                                      ; G                   ; yes                    ;
; 74373:inst|14                                      ; G                   ; yes                    ;
; 74373:inst|13                                      ; G                   ; yes                    ;
; 74373:inst|12                                      ; G                   ; yes                    ;
; Number of user-specified and inferred latches = 8  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Fri Mar 16 16:50:31 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off latch8 -c latch8
Info: Found 1 design units, including 1 entities, in source file latch8.bdf
    Info: Found entity 1: latch8
Info: Elaborating entity "latch8" for the top level hierarchy
Info: Found 1 design units, including 1 entities, in source file e:/altera60/quartus60/libraries/others/maxplus2/74373.bdf
    Info: Found entity 1: 74373
Info: Elaborating entity "74373" for hierarchy "74373:inst"
Info: Elaborated megafunction instantiation "74373:inst"
Info: Implemented 26 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 8 output pins
    Info: Implemented 8 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Fri Mar 16 16:50:37 2007
    Info: Elapsed time: 00:00:08