latch8.tan.summary

大量VHDL写的数字系统设计有用实例达到

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.734 ns
From           : D[5]
To             : 74373:inst|17
From Clock     : --
To Clock       : G
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 7.631 ns
From           : 74373:inst|17
To             : Q[5]
From Clock     : G
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 10.372 ns
From           : OE
To             : Q[5]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.325 ns
From           : D[3]
To             : 74373:inst|15
From Clock     : --
To Clock       : G
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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