piso4.tan.rpt

大量VHDL写的数字系统设计有用实例达到

; Slack ; Required tsu ; Actual tsu ; From   ; To   ; To Clock ;
+-------+--------------+------------+--------+------+----------+
; N/A   ; None         ; 5.113 ns   ; din[2] ; q[2] ; clk      ;
; N/A   ; None         ; 5.111 ns   ; din[1] ; q[1] ; clk      ;
; N/A   ; None         ; 4.492 ns   ; din[3] ; q[3] ; clk      ;
; N/A   ; None         ; 0.381 ns   ; din[0] ; q[0] ; clk      ;
+-------+--------------+------------+--------+------+----------+


+--------------------------------------------------------------+
; tco                                                          ;
+-------+--------------+------------+------+------+------------+
; Slack ; Required tco ; Actual tco ; From ; To   ; From Clock ;
+-------+--------------+------------+------+------+------------+
; N/A   ; None         ; 6.866 ns   ; q[3] ; dout ; clk        ;
+-------+--------------+------------+------+------+------------+


+--------------------------------------------------------------------+
; th                                                                 ;
+---------------+-------------+-----------+--------+------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To   ; To Clock ;
+---------------+-------------+-----------+--------+------+----------+
; N/A           ; None        ; -0.115 ns ; din[0] ; q[0] ; clk      ;
; N/A           ; None        ; -4.226 ns ; din[3] ; q[3] ; clk      ;
; N/A           ; None        ; -4.845 ns ; din[1] ; q[1] ; clk      ;
; N/A           ; None        ; -4.847 ns ; din[2] ; q[2] ; clk      ;
+---------------+-------------+-----------+--------+------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Jun 01 11:14:51 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off piso4 -c piso4 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 340.02 MHz between source register "cnt[0]" and destination register "q[1]"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.220 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y6_N19; Fanout = 6; REG Node = 'cnt[0]'
            Info: 2: + IC(0.488 ns) + CELL(0.624 ns) = 1.112 ns; Loc. = LCCOMB_X1_Y6_N4; Fanout = 1; COMB Node = 'q~190'
            Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.220 ns; Loc. = LCFF_X1_Y6_N5; Fanout = 1; REG Node = 'q[1]'
            Info: Total cell delay = 0.732 ns ( 60.00 % )
            Info: Total interconnect delay = 0.488 ns ( 40.00 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.801 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.906 ns) + CELL(0.666 ns) = 2.801 ns; Loc. = LCFF_X1_Y6_N5; Fanout = 1; REG Node = 'q[1]'
                Info: Total cell delay = 1.756 ns ( 62.69 % )
                Info: Total interconnect delay = 1.045 ns ( 37.31 % )
            Info: - Longest clock path from clock "clk" to source register is 2.801 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.906 ns) + CELL(0.666 ns) = 2.801 ns; Loc. = LCFF_X1_Y6_N19; Fanout = 6; REG Node = 'cnt[0]'
                Info: Total cell delay = 1.756 ns ( 62.69 % )
                Info: Total interconnect delay = 1.045 ns ( 37.31 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "q[2]" (data pin = "din[2]", clock pin = "clk") is 5.113 ns
    Info: + Longest pin to register delay is 7.954 ns
        Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_43; Fanout = 1; PIN Node = 'din[2]'
        Info: 2: + IC(6.251 ns) + CELL(0.651 ns) = 7.846 ns; Loc. = LCCOMB_X1_Y6_N16; Fanout = 1; COMB Node = 'q~189'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.954 ns; Loc. = LCFF_X1_Y6_N17; Fanout = 1; REG Node = 'q[2]'
        Info: Total cell delay = 1.703 ns ( 21.41 % )
        Info: Total interconnect delay = 6.251 ns ( 78.59 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.801 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.906 ns) + CELL(0.666 ns) = 2.801 ns; Loc. = LCFF_X1_Y6_N17; Fanout = 1; REG Node = 'q[2]'
        Info: Total cell delay = 1.756 ns ( 62.69 % )
        Info: Total interconnect delay = 1.045 ns ( 37.31 % )
Info: tco from clock "clk" to destination pin "dout" through register "q[3]" is 6.866 ns
    Info: + Longest clock path from clock "clk" to source register is 2.801 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.906 ns) + CELL(0.666 ns) = 2.801 ns; Loc. = LCFF_X1_Y6_N9; Fanout = 1; REG Node = 'q[3]'
        Info: Total cell delay = 1.756 ns ( 62.69 % )
        Info: Total interconnect delay = 1.045 ns ( 37.31 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 3.761 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y6_N9; Fanout = 1; REG Node = 'q[3]'
        Info: 2: + IC(0.705 ns) + CELL(3.056 ns) = 3.761 ns; Loc. = PIN_28; Fanout = 0; PIN Node = 'dout'
        Info: Total cell delay = 3.056 ns ( 81.25 % )
        Info: Total interconnect delay = 0.705 ns ( 18.75 % )
Info: th for register "q[0]" (data pin = "din[0]", clock pin = "clk") is -0.115 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.801 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.906 ns) + CELL(0.666 ns) = 2.801 ns; Loc. = LCFF_X1_Y6_N21; Fanout = 2; REG Node = 'q[0]'
        Info: Total cell delay = 1.756 ns ( 62.69 % )
        Info: Total interconnect delay = 1.045 ns ( 37.31 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 3.222 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_21; Fanout = 1; PIN Node = 'din[0]'
        Info: 2: + IC(1.373 ns) + CELL(0.651 ns) = 3.114 ns; Loc. = LCCOMB_X1_Y6_N20; Fanout = 1; COMB Node = 'q[0]~191'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 3.222 ns; Loc. = LCFF_X1_Y6_N21; Fanout = 2; REG Node = 'q[0]'
        Info: Total cell delay = 1.849 ns ( 57.39 % )
        Info: Total interconnect delay = 1.373 ns ( 42.61 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 103 megabytes of memory during processing
    Info: Processing ended: Fri Jun 01 11:14:53 2007
    Info: Elapsed time: 00:00:02