📄 mchange_1.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register q\[6\]~reg0 register q\[0\]~reg0 331.02 MHz 3.021 ns Internal " "Info: Clock \"clk\" has Internal fmax of 331.02 MHz between source register \"q\[6\]~reg0\" and destination register \"q\[0\]~reg0\" (period= 3.021 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.757 ns + Longest register register " "Info: + Longest register to register delay is 2.757 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q\[6\]~reg0 1 REG LCFF_X32_Y10_N15 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X32_Y10_N15; Fanout = 3; REG Node = 'q\[6\]~reg0'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { q[6]~reg0 } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.458 ns) + CELL(0.370 ns) 0.828 ns Equal0~63 2 COMB LCCOMB_X32_Y10_N0 1 " "Info: 2: + IC(0.458 ns) + CELL(0.370 ns) = 0.828 ns; Loc. = LCCOMB_X32_Y10_N0; Fanout = 1; COMB Node = 'Equal0~63'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.828 ns" { q[6]~reg0 Equal0~63 } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.364 ns) + CELL(0.580 ns) 1.772 ns Equal0~67 3 COMB LCCOMB_X32_Y10_N24 7 " "Info: 3: + IC(0.364 ns) + CELL(0.580 ns) = 1.772 ns; Loc. = LCCOMB_X32_Y10_N24; Fanout = 7; COMB Node = 'Equal0~67'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.944 ns" { Equal0~63 Equal0~67 } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.325 ns) + CELL(0.660 ns) 2.757 ns q\[0\]~reg0 4 REG LCFF_X32_Y10_N3 4 " "Info: 4: + IC(0.325 ns) + CELL(0.660 ns) = 2.757 ns; Loc. = LCFF_X32_Y10_N3; Fanout = 4; REG Node = 'q\[0\]~reg0'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.985 ns" { Equal0~67 q[0]~reg0 } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.610 ns ( 58.40 % ) " "Info: Total cell delay = 1.610 ns ( 58.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.147 ns ( 41.60 % ) " "Info: Total interconnect delay = 1.147 ns ( 41.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.757 ns" { q[6]~reg0 Equal0~63 Equal0~67 q[0]~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.757 ns" { q[6]~reg0 Equal0~63 Equal0~67 q[0]~reg0 } { 0.000ns 0.458ns 0.364ns 0.325ns } { 0.000ns 0.370ns 0.580ns 0.660ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.774 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.774 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.879 ns) + CELL(0.666 ns) 2.774 ns q\[0\]~reg0 3 REG LCFF_X32_Y10_N3 4 " "Info: 3: + IC(0.879 ns) + CELL(0.666 ns) = 2.774 ns; Loc. = LCFF_X32_Y10_N3; Fanout = 4; REG Node = 'q\[0\]~reg0'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.545 ns" { clk~clkctrl q[0]~reg0 } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.30 % ) " "Info: Total cell delay = 1.756 ns ( 63.30 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.018 ns ( 36.70 % ) " "Info: Total interconnect delay = 1.018 ns ( 36.70 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.774 ns" { clk clk~clkctrl q[0]~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.774 ns" { clk clk~combout clk~clkctrl q[0]~reg0 } { 0.000ns 0.000ns 0.139ns 0.879ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.774 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.774 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.879 ns) + CELL(0.666 ns) 2.774 ns q\[6\]~reg0 3 REG LCFF_X32_Y10_N15 3 " "Info: 3: + IC(0.879 ns) + CELL(0.666 ns) = 2.774 ns; Loc. = LCFF_X32_Y10_N15; Fanout = 3; REG Node = 'q\[6\]~reg0'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.545 ns" { clk~clkctrl q[6]~reg0 } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.30 % ) " "Info: Total cell delay = 1.756 ns ( 63.30 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.018 ns ( 36.70 % ) " "Info: Total interconnect delay = 1.018 ns ( 36.70 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.774 ns" { clk clk~clkctrl q[6]~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.774 ns" { clk clk~combout clk~clkctrl q[6]~reg0 } { 0.000ns 0.000ns 0.139ns 0.879ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.774 ns" { clk clk~clkctrl q[0]~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.774 ns" { clk clk~combout clk~clkctrl q[0]~reg0 } { 0.000ns 0.000ns 0.139ns 0.879ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.774 ns" { clk clk~clkctrl q[6]~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.774 ns" { clk clk~combout clk~clkctrl q[6]~reg0 } { 0.000ns 0.000ns 0.139ns 0.879ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 17 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 17 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.757 ns" { q[6]~reg0 Equal0~63 Equal0~67 q[0]~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.757 ns" { q[6]~reg0 Equal0~63 Equal0~67 q[0]~reg0 } { 0.000ns 0.458ns 0.364ns 0.325ns } { 0.000ns 0.370ns 0.580ns 0.660ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.774 ns" { clk clk~clkctrl q[0]~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.774 ns" { clk clk~combout clk~clkctrl q[0]~reg0 } { 0.000ns 0.000ns 0.139ns 0.879ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.774 ns" { clk clk~clkctrl q[6]~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.774 ns" { clk clk~combout clk~clkctrl q[6]~reg0 } { 0.000ns 0.000ns 0.139ns 0.879ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "q\[0\]~reg0 m\[5\] clk 9.084 ns register " "Info: tsu for register \"q\[0\]~reg0\" (data pin = \"m\[5\]\", clock pin = \"clk\") is 9.084 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.898 ns + Longest pin register " "Info: + Longest pin to register delay is 11.898 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns m\[5\] 1 PIN PIN_119 2 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_119; Fanout = 2; PIN Node = 'm\[5\]'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { m[5] } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.638 ns) + CELL(0.596 ns) 8.168 ns Add0~109 2 COMB LCCOMB_X33_Y10_N22 1 " "Info: 2: + IC(6.638 ns) + CELL(0.596 ns) = 8.168 ns; Loc. = LCCOMB_X33_Y10_N22; Fanout = 1; COMB Node = 'Add0~109'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "7.234 ns" { m[5] Add0~109 } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 8.674 ns Add0~110 3 COMB LCCOMB_X33_Y10_N24 1 " "Info: 3: + IC(0.000 ns) + CELL(0.506 ns) = 8.674 ns; Loc. = LCCOMB_X33_Y10_N24; Fanout = 1; COMB Node = 'Add0~110'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.506 ns" { Add0~109 Add0~110 } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.679 ns) + CELL(0.616 ns) 9.969 ns Equal0~63 4 COMB LCCOMB_X32_Y10_N0 1 " "Info: 4: + IC(0.679 ns) + CELL(0.616 ns) = 9.969 ns; Loc. = LCCOMB_X32_Y10_N0; Fanout = 1; COMB Node = 'Equal0~63'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.295 ns" { Add0~110 Equal0~63 } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.364 ns) + CELL(0.580 ns) 10.913 ns Equal0~67 5 COMB LCCOMB_X32_Y10_N24 7 " "Info: 5: + IC(0.364 ns) + CELL(0.580 ns) = 10.913 ns; Loc. = LCCOMB_X32_Y10_N24; Fanout = 7; COMB Node = 'Equal0~67'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.944 ns" { Equal0~63 Equal0~67 } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.325 ns) + CELL(0.660 ns) 11.898 ns q\[0\]~reg0 6 REG LCFF_X32_Y10_N3 4 " "Info: 6: + IC(0.325 ns) + CELL(0.660 ns) = 11.898 ns; Loc. = LCFF_X32_Y10_N3; Fanout = 4; REG Node = 'q\[0\]~reg0'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.985 ns" { Equal0~67 q[0]~reg0 } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.892 ns ( 32.71 % ) " "Info: Total cell delay = 3.892 ns ( 32.71 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.006 ns ( 67.29 % ) " "Info: Total interconnect delay = 8.006 ns ( 67.29 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "11.898 ns" { m[5] Add0~109 Add0~110 Equal0~63 Equal0~67 q[0]~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "11.898 ns" { m[5] m[5]~combout Add0~109 Add0~110 Equal0~63 Equal0~67 q[0]~reg0 } { 0.000ns 0.000ns 6.638ns 0.000ns 0.679ns 0.364ns 0.325ns } { 0.000ns 0.934ns 0.596ns 0.506ns 0.616ns 0.580ns 0.660ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 17 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.774 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.774 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.879 ns) + CELL(0.666 ns) 2.774 ns q\[0\]~reg0 3 REG LCFF_X32_Y10_N3 4 " "Info: 3: + IC(0.879 ns) + CELL(0.666 ns) = 2.774 ns; Loc. = LCFF_X32_Y10_N3; Fanout = 4; REG Node = 'q\[0\]~reg0'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.545 ns" { clk~clkctrl q[0]~reg0 } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.30 % ) " "Info: Total cell delay = 1.756 ns ( 63.30 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.018 ns ( 36.70 % ) " "Info: Total interconnect delay = 1.018 ns ( 36.70 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.774 ns" { clk clk~clkctrl q[0]~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.774 ns" { clk clk~combout clk~clkctrl q[0]~reg0 } { 0.000ns 0.000ns 0.139ns 0.879ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "11.898 ns" { m[5] Add0~109 Add0~110 Equal0~63 Equal0~67 q[0]~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "11.898 ns" { m[5] m[5]~combout Add0~109 Add0~110 Equal0~63 Equal0~67 q[0]~reg0 } { 0.000ns 0.000ns 6.638ns 0.000ns 0.679ns 0.364ns 0.325ns } { 0.000ns 0.934ns 0.596ns 0.506ns 0.616ns 0.580ns 0.660ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.774 ns" { clk clk~clkctrl q[0]~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.774 ns" { clk clk~combout clk~clkctrl q[0]~reg0 } { 0.000ns 0.000ns 0.139ns 0.879ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[1\] q\[1\]~reg0 8.457 ns register " "Info: tco from clock \"clk\" to destination pin \"q\[1\]\" through register \"q\[1\]~reg0\" is 8.457 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.774 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.774 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.879 ns) + CELL(0.666 ns) 2.774 ns q\[1\]~reg0 3 REG LCFF_X32_Y10_N5 4 " "Info: 3: + IC(0.879 ns) + CELL(0.666 ns) = 2.774 ns; Loc. = LCFF_X32_Y10_N5; Fanout = 4; REG Node = 'q\[1\]~reg0'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.545 ns" { clk~clkctrl q[1]~reg0 } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.30 % ) " "Info: Total cell delay = 1.756 ns ( 63.30 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.018 ns ( 36.70 % ) " "Info: Total interconnect delay = 1.018 ns ( 36.70 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.774 ns" { clk clk~clkctrl q[1]~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.774 ns" { clk clk~combout clk~clkctrl q[1]~reg0 } { 0.000ns 0.000ns 0.139ns 0.879ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 17 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.379 ns + Longest register pin " "Info: + Longest register to pin delay is 5.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q\[1\]~reg0 1 REG LCFF_X32_Y10_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X32_Y10_N5; Fanout = 4; REG Node = 'q\[1\]~reg0'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { q[1]~reg0 } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.143 ns) + CELL(3.236 ns) 5.379 ns q\[1\] 2 PIN PIN_64 0 " "Info: 2: + IC(2.143 ns) + CELL(3.236 ns) = 5.379 ns; Loc. = PIN_64; Fanout = 0; PIN Node = 'q\[1\]'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "5.379 ns" { q[1]~reg0 q[1] } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.236 ns ( 60.16 % ) " "Info: Total cell delay = 3.236 ns ( 60.16 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.143 ns ( 39.84 % ) " "Info: Total interconnect delay = 2.143 ns ( 39.84 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "5.379 ns" { q[1]~reg0 q[1] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "5.379 ns" { q[1]~reg0 q[1] } { 0.000ns 2.143ns } { 0.000ns 3.236ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.774 ns" { clk clk~clkctrl q[1]~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.774 ns" { clk clk~combout clk~clkctrl q[1]~reg0 } { 0.000ns 0.000ns 0.139ns 0.879ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "5.379 ns" { q[1]~reg0 q[1] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "5.379 ns" { q[1]~reg0 q[1] } { 0.000ns 2.143ns } { 0.000ns 3.236ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "q\[0\]~reg0 m\[1\] clk -2.022 ns register " "Info: th for register \"q\[0\]~reg0\" (data pin = \"m\[1\]\", clock pin = \"clk\") is -2.022 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.774 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.774 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.879 ns) + CELL(0.666 ns) 2.774 ns q\[0\]~reg0 3 REG LCFF_X32_Y10_N3 4 " "Info: 3: + IC(0.879 ns) + CELL(0.666 ns) = 2.774 ns; Loc. = LCFF_X32_Y10_N3; Fanout = 4; REG Node = 'q\[0\]~reg0'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.545 ns" { clk~clkctrl q[0]~reg0 } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.30 % ) " "Info: Total cell delay = 1.756 ns ( 63.30 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.018 ns ( 36.70 % ) " "Info: Total interconnect delay = 1.018 ns ( 36.70 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.774 ns" { clk clk~clkctrl q[0]~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.774 ns" { clk clk~combout clk~clkctrl q[0]~reg0 } { 0.000ns 0.000ns 0.139ns 0.879ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" { } { { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 17 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.102 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.102 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns m\[1\] 1 PIN PIN_88 2 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_88; Fanout = 2; PIN Node = 'm\[1\]'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { m[1] } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.470 ns) + CELL(0.589 ns) 2.169 ns Add0~100 2 COMB LCCOMB_X33_Y10_N14 1 " "Info: 2: + IC(0.470 ns) + CELL(0.589 ns) = 2.169 ns; Loc. = LCCOMB_X33_Y10_N14; Fanout = 1; COMB Node = 'Add0~100'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.059 ns" { m[1] Add0~100 } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.587 ns) + CELL(0.616 ns) 3.372 ns Equal0~65 3 COMB LCCOMB_X32_Y10_N20 1 " "Info: 3: + IC(0.587 ns) + CELL(0.616 ns) = 3.372 ns; Loc. = LCCOMB_X32_Y10_N20; Fanout = 1; COMB Node = 'Equal0~65'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.203 ns" { Add0~100 Equal0~65 } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.375 ns) + CELL(0.370 ns) 4.117 ns Equal0~67 4 COMB LCCOMB_X32_Y10_N24 7 " "Info: 4: + IC(0.375 ns) + CELL(0.370 ns) = 4.117 ns; Loc. = LCCOMB_X32_Y10_N24; Fanout = 7; COMB Node = 'Equal0~67'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.745 ns" { Equal0~65 Equal0~67 } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.325 ns) + CELL(0.660 ns) 5.102 ns q\[0\]~reg0 5 REG LCFF_X32_Y10_N3 4 " "Info: 5: + IC(0.325 ns) + CELL(0.660 ns) = 5.102 ns; Loc. = LCFF_X32_Y10_N3; Fanout = 4; REG Node = 'q\[0\]~reg0'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.985 ns" { Equal0~67 q[0]~reg0 } "NODE_NAME" } } { "mchange_1.vhd" "" { Text "D:/my_eda/mchange_1/mchange_1.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.345 ns ( 65.56 % ) " "Info: Total cell delay = 3.345 ns ( 65.56 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.757 ns ( 34.44 % ) " "Info: Total interconnect delay = 1.757 ns ( 34.44 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "5.102 ns" { m[1] Add0~100 Equal0~65 Equal0~67 q[0]~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "5.102 ns" { m[1] m[1]~combout Add0~100 Equal0~65 Equal0~67 q[0]~reg0 } { 0.000ns 0.000ns 0.470ns 0.587ns 0.375ns 0.325ns } { 0.000ns 1.110ns 0.589ns 0.616ns 0.370ns 0.660ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.774 ns" { clk clk~clkctrl q[0]~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.774 ns" { clk clk~combout clk~clkctrl q[0]~reg0 } { 0.000ns 0.000ns 0.139ns 0.879ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "5.102 ns" { m[1] Add0~100 Equal0~65 Equal0~67 q[0]~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "5.102 ns" { m[1] m[1]~combout Add0~100 Equal0~65 Equal0~67 q[0]~reg0 } { 0.000ns 0.000ns 0.470ns 0.587ns 0.375ns 0.325ns } { 0.000ns 1.110ns 0.589ns 0.616ns 0.370ns 0.660ns } } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -