mchange_1.tan.rpt

大量VHDL写的数字系统设计有用实例达到

; N/A           ; None        ; -6.879 ns ; m[3] ; q[4]~reg0 ; clk      ;
; N/A           ; None        ; -6.879 ns ; m[3] ; q[5]~reg0 ; clk      ;
; N/A           ; None        ; -6.950 ns ; m[6] ; q[0]~reg0 ; clk      ;
; N/A           ; None        ; -6.950 ns ; m[6] ; q[3]~reg0 ; clk      ;
; N/A           ; None        ; -6.950 ns ; m[6] ; q[6]~reg0 ; clk      ;
; N/A           ; None        ; -6.950 ns ; m[6] ; q[1]~reg0 ; clk      ;
; N/A           ; None        ; -6.950 ns ; m[6] ; q[2]~reg0 ; clk      ;
; N/A           ; None        ; -6.950 ns ; m[6] ; q[4]~reg0 ; clk      ;
; N/A           ; None        ; -6.950 ns ; m[6] ; q[5]~reg0 ; clk      ;
; N/A           ; None        ; -7.044 ns ; m[4] ; q[0]~reg0 ; clk      ;
; N/A           ; None        ; -7.044 ns ; m[4] ; q[3]~reg0 ; clk      ;
; N/A           ; None        ; -7.044 ns ; m[4] ; q[6]~reg0 ; clk      ;
; N/A           ; None        ; -7.044 ns ; m[4] ; q[1]~reg0 ; clk      ;
; N/A           ; None        ; -7.044 ns ; m[4] ; q[2]~reg0 ; clk      ;
; N/A           ; None        ; -7.044 ns ; m[4] ; q[4]~reg0 ; clk      ;
; N/A           ; None        ; -7.044 ns ; m[4] ; q[5]~reg0 ; clk      ;
; N/A           ; None        ; -7.885 ns ; m[2] ; q[0]~reg0 ; clk      ;
; N/A           ; None        ; -7.885 ns ; m[2] ; q[3]~reg0 ; clk      ;
; N/A           ; None        ; -7.885 ns ; m[2] ; q[6]~reg0 ; clk      ;
; N/A           ; None        ; -7.885 ns ; m[2] ; q[1]~reg0 ; clk      ;
; N/A           ; None        ; -7.885 ns ; m[2] ; q[2]~reg0 ; clk      ;
; N/A           ; None        ; -7.885 ns ; m[2] ; q[4]~reg0 ; clk      ;
; N/A           ; None        ; -7.885 ns ; m[2] ; q[5]~reg0 ; clk      ;
; N/A           ; None        ; -7.995 ns ; m[5] ; q[0]~reg0 ; clk      ;
; N/A           ; None        ; -7.995 ns ; m[5] ; q[3]~reg0 ; clk      ;
; N/A           ; None        ; -7.995 ns ; m[5] ; q[6]~reg0 ; clk      ;
; N/A           ; None        ; -7.995 ns ; m[5] ; q[1]~reg0 ; clk      ;
; N/A           ; None        ; -7.995 ns ; m[5] ; q[2]~reg0 ; clk      ;
; N/A           ; None        ; -7.995 ns ; m[5] ; q[4]~reg0 ; clk      ;
; N/A           ; None        ; -7.995 ns ; m[5] ; q[5]~reg0 ; clk      ;
+---------------+-------------+-----------+------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Fri Mar 16 09:49:04 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mchange_1 -c mchange_1 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 331.02 MHz between source register "q[6]~reg0" and destination register "q[0]~reg0" (period= 3.021 ns)
    Info: + Longest register to register delay is 2.757 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X32_Y10_N15; Fanout = 3; REG Node = 'q[6]~reg0'
        Info: 2: + IC(0.458 ns) + CELL(0.370 ns) = 0.828 ns; Loc. = LCCOMB_X32_Y10_N0; Fanout = 1; COMB Node = 'Equal0~63'
        Info: 3: + IC(0.364 ns) + CELL(0.580 ns) = 1.772 ns; Loc. = LCCOMB_X32_Y10_N24; Fanout = 7; COMB Node = 'Equal0~67'
        Info: 4: + IC(0.325 ns) + CELL(0.660 ns) = 2.757 ns; Loc. = LCFF_X32_Y10_N3; Fanout = 4; REG Node = 'q[0]~reg0'
        Info: Total cell delay = 1.610 ns ( 58.40 % )
        Info: Total interconnect delay = 1.147 ns ( 41.60 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.774 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.879 ns) + CELL(0.666 ns) = 2.774 ns; Loc. = LCFF_X32_Y10_N3; Fanout = 4; REG Node = 'q[0]~reg0'
            Info: Total cell delay = 1.756 ns ( 63.30 % )
            Info: Total interconnect delay = 1.018 ns ( 36.70 % )
        Info: - Longest clock path from clock "clk" to source register is 2.774 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.879 ns) + CELL(0.666 ns) = 2.774 ns; Loc. = LCFF_X32_Y10_N15; Fanout = 3; REG Node = 'q[6]~reg0'
            Info: Total cell delay = 1.756 ns ( 63.30 % )
            Info: Total interconnect delay = 1.018 ns ( 36.70 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "q[0]~reg0" (data pin = "m[5]", clock pin = "clk") is 9.084 ns
    Info: + Longest pin to register delay is 11.898 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_119; Fanout = 2; PIN Node = 'm[5]'
        Info: 2: + IC(6.638 ns) + CELL(0.596 ns) = 8.168 ns; Loc. = LCCOMB_X33_Y10_N22; Fanout = 1; COMB Node = 'Add0~109'
        Info: 3: + IC(0.000 ns) + CELL(0.506 ns) = 8.674 ns; Loc. = LCCOMB_X33_Y10_N24; Fanout = 1; COMB Node = 'Add0~110'
        Info: 4: + IC(0.679 ns) + CELL(0.616 ns) = 9.969 ns; Loc. = LCCOMB_X32_Y10_N0; Fanout = 1; COMB Node = 'Equal0~63'
        Info: 5: + IC(0.364 ns) + CELL(0.580 ns) = 10.913 ns; Loc. = LCCOMB_X32_Y10_N24; Fanout = 7; COMB Node = 'Equal0~67'
        Info: 6: + IC(0.325 ns) + CELL(0.660 ns) = 11.898 ns; Loc. = LCFF_X32_Y10_N3; Fanout = 4; REG Node = 'q[0]~reg0'
        Info: Total cell delay = 3.892 ns ( 32.71 % )
        Info: Total interconnect delay = 8.006 ns ( 67.29 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.774 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.879 ns) + CELL(0.666 ns) = 2.774 ns; Loc. = LCFF_X32_Y10_N3; Fanout = 4; REG Node = 'q[0]~reg0'
        Info: Total cell delay = 1.756 ns ( 63.30 % )
        Info: Total interconnect delay = 1.018 ns ( 36.70 % )
Info: tco from clock "clk" to destination pin "q[1]" through register "q[1]~reg0" is 8.457 ns
    Info: + Longest clock path from clock "clk" to source register is 2.774 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.879 ns) + CELL(0.666 ns) = 2.774 ns; Loc. = LCFF_X32_Y10_N5; Fanout = 4; REG Node = 'q[1]~reg0'
        Info: Total cell delay = 1.756 ns ( 63.30 % )
        Info: Total interconnect delay = 1.018 ns ( 36.70 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 5.379 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X32_Y10_N5; Fanout = 4; REG Node = 'q[1]~reg0'
        Info: 2: + IC(2.143 ns) + CELL(3.236 ns) = 5.379 ns; Loc. = PIN_64; Fanout = 0; PIN Node = 'q[1]'
        Info: Total cell delay = 3.236 ns ( 60.16 % )
        Info: Total interconnect delay = 2.143 ns ( 39.84 % )
Info: th for register "q[0]~reg0" (data pin = "m[1]", clock pin = "clk") is -2.022 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.774 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.879 ns) + CELL(0.666 ns) = 2.774 ns; Loc. = LCFF_X32_Y10_N3; Fanout = 4; REG Node = 'q[0]~reg0'
        Info: Total cell delay = 1.756 ns ( 63.30 % )
        Info: Total interconnect delay = 1.018 ns ( 36.70 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 5.102 ns
        Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_88; Fanout = 2; PIN Node = 'm[1]'
        Info: 2: + IC(0.470 ns) + CELL(0.589 ns) = 2.169 ns; Loc. = LCCOMB_X33_Y10_N14; Fanout = 1; COMB Node = 'Add0~100'
        Info: 3: + IC(0.587 ns) + CELL(0.616 ns) = 3.372 ns; Loc. = LCCOMB_X32_Y10_N20; Fanout = 1; COMB Node = 'Equal0~65'
        Info: 4: + IC(0.375 ns) + CELL(0.370 ns) = 4.117 ns; Loc. = LCCOMB_X32_Y10_N24; Fanout = 7; COMB Node = 'Equal0~67'
        Info: 5: + IC(0.325 ns) + CELL(0.660 ns) = 5.102 ns; Loc. = LCFF_X32_Y10_N3; Fanout = 4; REG Node = 'q[0]~reg0'
        Info: Total cell delay = 3.345 ns ( 65.56 % )
        Info: Total interconnect delay = 1.757 ns ( 34.44 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Mar 16 09:49:05 2007
    Info: Elapsed time: 00:00:02