nand_2.tan.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Feb 12 20:47:30 2007 " "Info: Processing started: Mon Feb 12 20:47:30 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off nand_2 -c nand_2 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off nand_2 -c nand_2 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "b y 12.710 ns Longest " "Info: Longest tpd from source pin \"b\" to destination pin \"y\" is 12.710 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.924 ns) 0.924 ns b 1 PIN PIN_57 1 " "Info: 1: + IC(0.000 ns) + CELL(0.924 ns) = 0.924 ns; Loc. = PIN_57; Fanout = 1; PIN Node = 'b'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { b } "NODE_NAME" } } { "nand_2.vhd" "" { Text "D:/my_eda/nand/nand2/nand_2.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.728 ns) + CELL(0.615 ns) 7.267 ns y~0 2 COMB LCCOMB_X16_Y1_N2 1 " "Info: 2: + IC(5.728 ns) + CELL(0.615 ns) = 7.267 ns; Loc. = LCCOMB_X16_Y1_N2; Fanout = 1; COMB Node = 'y~0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.343 ns" { b y~0 } "NODE_NAME" } } { "nand_2.vhd" "" { Text "D:/my_eda/nand/nand2/nand_2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.387 ns) + CELL(3.056 ns) 12.710 ns y 3 PIN PIN_73 0 " "Info: 3: + IC(2.387 ns) + CELL(3.056 ns) = 12.710 ns; Loc. = PIN_73; Fanout = 0; PIN Node = 'y'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.443 ns" { y~0 y } "NODE_NAME" } } { "nand_2.vhd" "" { Text "D:/my_eda/nand/nand2/nand_2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.595 ns ( 36.15 % ) " "Info: Total cell delay = 4.595 ns ( 36.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.115 ns ( 63.85 % ) " "Info: Total interconnect delay = 8.115 ns ( 63.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.710 ns" { b y~0 y } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.710 ns" { b b~combout y~0 y } { 0.000ns 0.000ns 5.728ns 2.387ns } { 0.000ns 0.924ns 0.615ns 3.056ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Feb 12 20:47:30 2007 " "Info: Processing ended: Mon Feb 12 20:47:30 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}