jk.fit.smsg

大量VHDL写的数字系统设计有用实例达到

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sun May 27 20:53:27 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off Jk -c Jk
Info: Selected device EP2C8T144C8 for design "Jk"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C5T144C8 is compatible
    Info: Device EP2C5T144I8 is compatible
    Info: Device EP2C8T144I8 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location 1
    Info: Pin ~nCSO~ is reserved at location 2
    Info: Pin ~LVDS54p/nCEO~ is reserved at location 76
Warning: No exact pin location assignment(s) for 7 pins of 7 total pins
    Info: Pin q not assigned to an exact location on the device
    Info: Pin qn not assigned to an exact location on the device
    Info: Pin r not assigned to an exact location on the device
    Info: Pin s not assigned to an exact location on the device
    Info: Pin k not assigned to an exact location on the device
    Info: Pin j not assigned to an exact location on the device
    Info: Pin cp not assigned to an exact location on the device
Info: Automatically promoted node cp (placed in PIN 17 (CLK0, LVDSCLK0p, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
Info: Automatically promoted node q_temp~262 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 6 (unused VREF, 3.30 VCCIO, 4 input, 2 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  14 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  23 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  20 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 1.800 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X1_Y9; Fanout = 1; REG Node = 'q_temp~_emulated'
    Info: 2: + IC(0.257 ns) + CELL(0.624 ns) = 0.881 ns; Loc. = LAB_X1_Y9; Fanout = 2; COMB Node = 'q_temp~260'
    Info: 3: + IC(0.187 ns) + CELL(0.624 ns) = 1.692 ns; Loc. = LAB_X1_Y9; Fanout = 1; COMB Node = 'q_temp~261'
    Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 1.800 ns; Loc. = LAB_X1_Y9; Fanout = 1; REG Node = 'q_temp~_emulated'
    Info: Total cell delay = 1.356 ns ( 75.33 % )
    Info: Total interconnect delay = 0.444 ns ( 24.67 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X0_Y10 to location X10_Y19
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 2 output pins without output pin load capacitance assignment
    Info: Pin "q" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "qn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
    Info: Allocated 175 megabytes of memory during processing
    Info: Processing ended: Sun May 27 20:53:37 2007
    Info: Elapsed time: 00:00:10