jk.tan.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Info" "ITDB_FULL_TPD_RESULT" "s q 12.055 ns Longest " "Info: Longest tpd from source pin \"s\" to destination pin \"q\" is 12.055 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns s 1 PIN PIN_142 6 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_142; Fanout = 6; PIN Node = 's'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { s } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.302 ns) + CELL(0.370 ns) 7.616 ns q_temp~260 2 COMB LCCOMB_X1_Y9_N18 2 " "Info: 2: + IC(6.302 ns) + CELL(0.370 ns) = 7.616 ns; Loc. = LCCOMB_X1_Y9_N18; Fanout = 2; COMB Node = 'q_temp~260'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.672 ns" { s q_temp~260 } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.383 ns) + CELL(3.056 ns) 12.055 ns q 3 PIN PIN_8 0 " "Info: 3: + IC(1.383 ns) + CELL(3.056 ns) = 12.055 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'q'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.439 ns" { q_temp~260 q } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.370 ns ( 36.25 % ) " "Info: Total cell delay = 4.370 ns ( 36.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.685 ns ( 63.75 % ) " "Info: Total interconnect delay = 7.685 ns ( 63.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "12.055 ns" { s q_temp~260 q } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "12.055 ns" { s s~combout q_temp~260 q } { 0.000ns 0.000ns 6.302ns 1.383ns } { 0.000ns 0.944ns 0.370ns 3.056ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "q_temp~_emulated j cp 0.902 ns register " "Info: th for register \"q_temp~_emulated\" (data pin = \"j\", clock pin = \"cp\") is 0.902 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp destination 2.766 ns + Longest register " "Info: + Longest clock path from clock \"cp\" to destination register is 2.766 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns cp 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'cp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cp } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns cp~clkctrl 2 COMB CLKCTRL_G2 2 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'cp~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { cp cp~clkctrl } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.871 ns) + CELL(0.666 ns) 2.766 ns q_temp~_emulated 3 REG LCFF_X1_Y9_N7 1 " "Info: 3: + IC(0.871 ns) + CELL(0.666 ns) = 2.766 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 1; REG Node = 'q_temp~_emulated'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.537 ns" { cp~clkctrl q_temp~_emulated } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.49 % ) " "Info: Total cell delay = 1.756 ns ( 63.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.010 ns ( 36.51 % ) " "Info: Total interconnect delay = 1.010 ns ( 36.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.766 ns" { cp cp~clkctrl q_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.766 ns" { cp cp~combout cp~clkctrl q_temp~_emulated } { 0.000ns 0.000ns 0.139ns 0.871ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.170 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns j 1 PIN PIN_21 3 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_21; Fanout = 3; PIN Node = 'j'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { j } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.370 ns) 2.062 ns q_temp~261 2 COMB LCCOMB_X1_Y9_N6 1 " "Info: 2: + IC(0.602 ns) + CELL(0.370 ns) = 2.062 ns; Loc. = LCCOMB_X1_Y9_N6; Fanout = 1; COMB Node = 'q_temp~261'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.972 ns" { j q_temp~261 } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.170 ns q_temp~_emulated 3 REG LCFF_X1_Y9_N7 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.170 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 1; REG Node = 'q_temp~_emulated'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { q_temp~261 q_temp~_emulated } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.568 ns ( 72.26 % ) " "Info: Total cell delay = 1.568 ns ( 72.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 27.74 % ) " "Info: Total interconnect delay = 0.602 ns ( 27.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.170 ns" { j q_temp~261 q_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.170 ns" { j j~combout q_temp~261 q_temp~_emulated } { 0.000ns 0.000ns 0.602ns 0.000ns } { 0.000ns 1.090ns 0.370ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.766 ns" { cp cp~clkctrl q_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.766 ns" { cp cp~combout cp~clkctrl q_temp~_emulated } { 0.000ns 0.000ns 0.139ns 0.871ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.170 ns" { j q_temp~261 q_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.170 ns" { j j~combout q_temp~261 q_temp~_emulated } { 0.000ns 0.000ns 0.602ns 0.000ns } { 0.000ns 1.090ns 0.370ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 4 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "103 " "Info: Allocated 103 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 27 20:54:05 2007 " "Info: Processing ended: Sun May 27 20:54:05 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}