jk.tan.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "cp " "Info: Assuming node \"cp\" is an undefined clock" {  } { { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 5 -1 0 } } { "e:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "cp" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "cp register register q_temp~_emulated q_temp~_emulated 340.02 MHz Internal " "Info: Clock \"cp\" Internal fmax is restricted to 340.02 MHz between source register \"q_temp~_emulated\" and destination register \"q_temp~_emulated\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.941 ns " "Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.333 ns + Longest register register " "Info: + Longest register to register delay is 1.333 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q_temp~_emulated 1 REG LCFF_X1_Y9_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 1; REG Node = 'q_temp~_emulated'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { q_temp~_emulated } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.206 ns) 0.643 ns q_temp~260 2 COMB LCCOMB_X1_Y9_N18 2 " "Info: 2: + IC(0.437 ns) + CELL(0.206 ns) = 0.643 ns; Loc. = LCCOMB_X1_Y9_N18; Fanout = 2; COMB Node = 'q_temp~260'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.643 ns" { q_temp~_emulated q_temp~260 } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.376 ns) + CELL(0.206 ns) 1.225 ns q_temp~261 3 COMB LCCOMB_X1_Y9_N6 1 " "Info: 3: + IC(0.376 ns) + CELL(0.206 ns) = 1.225 ns; Loc. = LCCOMB_X1_Y9_N6; Fanout = 1; COMB Node = 'q_temp~261'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.582 ns" { q_temp~260 q_temp~261 } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.333 ns q_temp~_emulated 4 REG LCFF_X1_Y9_N7 1 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 1.333 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 1; REG Node = 'q_temp~_emulated'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { q_temp~261 q_temp~_emulated } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.520 ns ( 39.01 % ) " "Info: Total cell delay = 0.520 ns ( 39.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.813 ns ( 60.99 % ) " "Info: Total interconnect delay = 0.813 ns ( 60.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.333 ns" { q_temp~_emulated q_temp~260 q_temp~261 q_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.333 ns" { q_temp~_emulated q_temp~260 q_temp~261 q_temp~_emulated } { 0.000ns 0.437ns 0.376ns 0.000ns } { 0.000ns 0.206ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp destination 2.766 ns + Shortest register " "Info: + Shortest clock path from clock \"cp\" to destination register is 2.766 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns cp 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'cp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cp } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns cp~clkctrl 2 COMB CLKCTRL_G2 2 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'cp~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { cp cp~clkctrl } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.871 ns) + CELL(0.666 ns) 2.766 ns q_temp~_emulated 3 REG LCFF_X1_Y9_N7 1 " "Info: 3: + IC(0.871 ns) + CELL(0.666 ns) = 2.766 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 1; REG Node = 'q_temp~_emulated'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.537 ns" { cp~clkctrl q_temp~_emulated } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.49 % ) " "Info: Total cell delay = 1.756 ns ( 63.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.010 ns ( 36.51 % ) " "Info: Total interconnect delay = 1.010 ns ( 36.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.766 ns" { cp cp~clkctrl q_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.766 ns" { cp cp~combout cp~clkctrl q_temp~_emulated } { 0.000ns 0.000ns 0.139ns 0.871ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp source 2.766 ns - Longest register " "Info: - Longest clock path from clock \"cp\" to source register is 2.766 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns cp 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'cp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cp } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns cp~clkctrl 2 COMB CLKCTRL_G2 2 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'cp~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { cp cp~clkctrl } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.871 ns) + CELL(0.666 ns) 2.766 ns q_temp~_emulated 3 REG LCFF_X1_Y9_N7 1 " "Info: 3: + IC(0.871 ns) + CELL(0.666 ns) = 2.766 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 1; REG Node = 'q_temp~_emulated'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.537 ns" { cp~clkctrl q_temp~_emulated } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.49 % ) " "Info: Total cell delay = 1.756 ns ( 63.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.010 ns ( 36.51 % ) " "Info: Total interconnect delay = 1.010 ns ( 36.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.766 ns" { cp cp~clkctrl q_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.766 ns" { cp cp~combout cp~clkctrl q_temp~_emulated } { 0.000ns 0.000ns 0.139ns 0.871ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.766 ns" { cp cp~clkctrl q_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.766 ns" { cp cp~combout cp~clkctrl q_temp~_emulated } { 0.000ns 0.000ns 0.139ns 0.871ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.766 ns" { cp cp~clkctrl q_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.766 ns" { cp cp~combout cp~clkctrl q_temp~_emulated } { 0.000ns 0.000ns 0.139ns 0.871ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.333 ns" { q_temp~_emulated q_temp~260 q_temp~261 q_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.333 ns" { q_temp~_emulated q_temp~260 q_temp~261 q_temp~_emulated } { 0.000ns 0.437ns 0.376ns 0.000ns } { 0.000ns 0.206ns 0.206ns 0.108ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.766 ns" { cp cp~clkctrl q_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.766 ns" { cp cp~combout cp~clkctrl q_temp~_emulated } { 0.000ns 0.000ns 0.139ns 0.871ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.766 ns" { cp cp~clkctrl q_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.766 ns" { cp cp~combout cp~clkctrl q_temp~_emulated } { 0.000ns 0.000ns 0.139ns 0.871ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { q_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { q_temp~_emulated } {  } {  } "" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 13 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "q_temp~_emulated s cp 6.233 ns register " "Info: tsu for register \"q_temp~_emulated\" (data pin = \"s\", clock pin = \"cp\") is 6.233 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.039 ns + Longest pin register " "Info: + Longest pin to register delay is 9.039 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns s 1 PIN PIN_142 6 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_142; Fanout = 6; PIN Node = 's'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { s } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.300 ns) + CELL(0.624 ns) 7.868 ns q_temp~263 2 COMB LCCOMB_X1_Y9_N16 2 " "Info: 2: + IC(6.300 ns) + CELL(0.624 ns) = 7.868 ns; Loc. = LCCOMB_X1_Y9_N16; Fanout = 2; COMB Node = 'q_temp~263'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.924 ns" { s q_temp~263 } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.316 ns) + CELL(0.855 ns) 9.039 ns q_temp~_emulated 3 REG LCFF_X1_Y9_N7 1 " "Info: 3: + IC(0.316 ns) + CELL(0.855 ns) = 9.039 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 1; REG Node = 'q_temp~_emulated'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.171 ns" { q_temp~263 q_temp~_emulated } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.423 ns ( 26.81 % ) " "Info: Total cell delay = 2.423 ns ( 26.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.616 ns ( 73.19 % ) " "Info: Total interconnect delay = 6.616 ns ( 73.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.039 ns" { s q_temp~263 q_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.039 ns" { s s~combout q_temp~263 q_temp~_emulated } { 0.000ns 0.000ns 6.300ns 0.316ns } { 0.000ns 0.944ns 0.624ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp destination 2.766 ns - Shortest register " "Info: - Shortest clock path from clock \"cp\" to destination register is 2.766 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns cp 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'cp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cp } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns cp~clkctrl 2 COMB CLKCTRL_G2 2 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'cp~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { cp cp~clkctrl } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.871 ns) + CELL(0.666 ns) 2.766 ns q_temp~_emulated 3 REG LCFF_X1_Y9_N7 1 " "Info: 3: + IC(0.871 ns) + CELL(0.666 ns) = 2.766 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 1; REG Node = 'q_temp~_emulated'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.537 ns" { cp~clkctrl q_temp~_emulated } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.49 % ) " "Info: Total cell delay = 1.756 ns ( 63.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.010 ns ( 36.51 % ) " "Info: Total interconnect delay = 1.010 ns ( 36.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.766 ns" { cp cp~clkctrl q_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.766 ns" { cp cp~combout cp~clkctrl q_temp~_emulated } { 0.000ns 0.000ns 0.139ns 0.871ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.039 ns" { s q_temp~263 q_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.039 ns" { s s~combout q_temp~263 q_temp~_emulated } { 0.000ns 0.000ns 6.300ns 0.316ns } { 0.000ns 0.944ns 0.624ns 0.855ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.766 ns" { cp cp~clkctrl q_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.766 ns" { cp cp~combout cp~clkctrl q_temp~_emulated } { 0.000ns 0.000ns 0.139ns 0.871ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "cp q q_temp~_emulated 8.152 ns register " "Info: tco from clock \"cp\" to destination pin \"q\" through register \"q_temp~_emulated\" is 8.152 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp source 2.766 ns + Longest register " "Info: + Longest clock path from clock \"cp\" to source register is 2.766 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns cp 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'cp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cp } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns cp~clkctrl 2 COMB CLKCTRL_G2 2 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'cp~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { cp cp~clkctrl } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.871 ns) + CELL(0.666 ns) 2.766 ns q_temp~_emulated 3 REG LCFF_X1_Y9_N7 1 " "Info: 3: + IC(0.871 ns) + CELL(0.666 ns) = 2.766 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 1; REG Node = 'q_temp~_emulated'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.537 ns" { cp~clkctrl q_temp~_emulated } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.49 % ) " "Info: Total cell delay = 1.756 ns ( 63.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.010 ns ( 36.51 % ) " "Info: Total interconnect delay = 1.010 ns ( 36.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.766 ns" { cp cp~clkctrl q_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.766 ns" { cp cp~combout cp~clkctrl q_temp~_emulated } { 0.000ns 0.000ns 0.139ns 0.871ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.082 ns + Longest register pin " "Info: + Longest register to pin delay is 5.082 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q_temp~_emulated 1 REG LCFF_X1_Y9_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 1; REG Node = 'q_temp~_emulated'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { q_temp~_emulated } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.206 ns) 0.643 ns q_temp~260 2 COMB LCCOMB_X1_Y9_N18 2 " "Info: 2: + IC(0.437 ns) + CELL(0.206 ns) = 0.643 ns; Loc. = LCCOMB_X1_Y9_N18; Fanout = 2; COMB Node = 'q_temp~260'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.643 ns" { q_temp~_emulated q_temp~260 } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.383 ns) + CELL(3.056 ns) 5.082 ns q 3 PIN PIN_8 0 " "Info: 3: + IC(1.383 ns) + CELL(3.056 ns) = 5.082 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'q'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.439 ns" { q_temp~260 q } "NODE_NAME" } } { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.262 ns ( 64.19 % ) " "Info: Total cell delay = 3.262 ns ( 64.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.820 ns ( 35.81 % ) " "Info: Total interconnect delay = 1.820 ns ( 35.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.082 ns" { q_temp~_emulated q_temp~260 q } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.082 ns" { q_temp~_emulated q_temp~260 q } { 0.000ns 0.437ns 1.383ns } { 0.000ns 0.206ns 3.056ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.766 ns" { cp cp~clkctrl q_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.766 ns" { cp cp~combout cp~clkctrl q_temp~_emulated } { 0.000ns 0.000ns 0.139ns 0.871ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.082 ns" { q_temp~_emulated q_temp~260 q } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.082 ns" { q_temp~_emulated q_temp~260 q } { 0.000ns 0.437ns 1.383ns } { 0.000ns 0.206ns 3.056ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}