cnt4.vhd

大量VHDL写的数字系统设计有用实例达到

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt4 is
port(clk:in std_logic;
     rst:in std_logic;
     en:in std_logic;
     q:out std_logic_vector(3 downto 0));
end;
architecture one of cnt4 is
   signal q1:std_logic_vector(3 downto 0);
begin
Process(clk,en,rst)
begin
if en='1' then
   if rst='1' then q1<="0000";
   elsif clk'event and clk='1' then 
	    q1<=q1+1;
   end if;
end if;
end process;
q<=q1;
end;