cnt4_top.tan.rpt

大量VHDL写的数字系统设计有用实例达到

; N/A   ; None         ; 8.963 ns   ; cnt4:inst1|q1[0] ; y[1] ; clk        ;
; N/A   ; None         ; 8.903 ns   ; cnt4:inst1|q1[2] ; y[1] ; clk        ;
; N/A   ; None         ; 8.894 ns   ; cnt4:inst1|q1[2] ; y[5] ; clk        ;
; N/A   ; None         ; 8.638 ns   ; cnt4:inst1|q1[0] ; y[7] ; clk        ;
; N/A   ; None         ; 8.637 ns   ; cnt4:inst1|q1[0] ; y[3] ; clk        ;
; N/A   ; None         ; 8.636 ns   ; cnt4:inst1|q1[1] ; y[3] ; clk        ;
; N/A   ; None         ; 8.591 ns   ; cnt4:inst1|q1[1] ; y[7] ; clk        ;
; N/A   ; None         ; 8.571 ns   ; cnt4:inst1|q1[2] ; y[3] ; clk        ;
; N/A   ; None         ; 8.564 ns   ; cnt4:inst1|q1[2] ; y[7] ; clk        ;
; N/A   ; None         ; 8.494 ns   ; cnt4:inst1|q1[3] ; y[5] ; clk        ;
; N/A   ; None         ; 8.473 ns   ; cnt4:inst1|q1[3] ; y[1] ; clk        ;
; N/A   ; None         ; 8.379 ns   ; cnt4:inst1|q1[0] ; y[6] ; clk        ;
; N/A   ; None         ; 8.370 ns   ; cnt4:inst1|q1[1] ; y[6] ; clk        ;
; N/A   ; None         ; 8.313 ns   ; cnt4:inst1|q1[2] ; y[6] ; clk        ;
; N/A   ; None         ; 8.140 ns   ; cnt4:inst1|q1[3] ; y[3] ; clk        ;
; N/A   ; None         ; 8.139 ns   ; cnt4:inst1|q1[3] ; y[7] ; clk        ;
; N/A   ; None         ; 7.975 ns   ; cnt4:inst1|q1[0] ; y[4] ; clk        ;
; N/A   ; None         ; 7.968 ns   ; cnt4:inst1|q1[1] ; y[4] ; clk        ;
; N/A   ; None         ; 7.961 ns   ; cnt4:inst1|q1[1] ; y[2] ; clk        ;
; N/A   ; None         ; 7.960 ns   ; cnt4:inst1|q1[0] ; y[2] ; clk        ;
; N/A   ; None         ; 7.911 ns   ; cnt4:inst1|q1[2] ; y[4] ; clk        ;
; N/A   ; None         ; 7.896 ns   ; cnt4:inst1|q1[2] ; y[2] ; clk        ;
; N/A   ; None         ; 7.879 ns   ; cnt4:inst1|q1[3] ; y[6] ; clk        ;
; N/A   ; None         ; 7.477 ns   ; cnt4:inst1|q1[3] ; y[4] ; clk        ;
; N/A   ; None         ; 7.465 ns   ; cnt4:inst1|q1[3] ; y[2] ; clk        ;
+-------+--------------+------------+------------------+------+------------+


+------------------------------------------------------------------------------+
; th                                                                           ;
+---------------+-------------+-----------+------+------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To               ; To Clock ;
+---------------+-------------+-----------+------+------------------+----------+
; N/A           ; None        ; 0.664 ns  ; en   ; cnt4:inst1|q1[0] ; clk      ;
; N/A           ; None        ; 0.664 ns  ; en   ; cnt4:inst1|q1[2] ; clk      ;
; N/A           ; None        ; 0.237 ns  ; en   ; cnt4:inst1|q1[1] ; clk      ;
; N/A           ; None        ; -0.329 ns ; en   ; cnt4:inst1|q1[3] ; clk      ;
+---------------+-------------+-----------+------+------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri May 18 22:41:49 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cnt4_top -c cnt4_top --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 340.02 MHz between source register "cnt4:inst1|q1[0]" and destination register "cnt4:inst1|q1[2]"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.491 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y8_N19; Fanout = 11; REG Node = 'cnt4:inst1|q1[0]'
            Info: 2: + IC(0.759 ns) + CELL(0.624 ns) = 1.383 ns; Loc. = LCCOMB_X1_Y8_N22; Fanout = 1; COMB Node = 'cnt4:inst1|q1[2]~150'
            Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.491 ns; Loc. = LCFF_X1_Y8_N23; Fanout = 9; REG Node = 'cnt4:inst1|q1[2]'
            Info: Total cell delay = 0.732 ns ( 49.09 % )
            Info: Total interconnect delay = 0.759 ns ( 50.91 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.785 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.890 ns) + CELL(0.666 ns) = 2.785 ns; Loc. = LCFF_X1_Y8_N23; Fanout = 9; REG Node = 'cnt4:inst1|q1[2]'
                Info: Total cell delay = 1.756 ns ( 63.05 % )
                Info: Total interconnect delay = 1.029 ns ( 36.95 % )
            Info: - Longest clock path from clock "clk" to source register is 2.785 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.890 ns) + CELL(0.666 ns) = 2.785 ns; Loc. = LCFF_X1_Y8_N19; Fanout = 11; REG Node = 'cnt4:inst1|q1[0]'
                Info: Total cell delay = 1.756 ns ( 63.05 % )
                Info: Total interconnect delay = 1.029 ns ( 36.95 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "cnt4:inst1|q1[3]" (data pin = "en", clock pin = "clk") is 0.595 ns
    Info: + Longest pin to register delay is 3.420 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 5; PIN Node = 'en'
        Info: 2: + IC(1.029 ns) + CELL(0.589 ns) = 2.708 ns; Loc. = LCCOMB_X1_Y8_N10; Fanout = 1; COMB Node = 'cnt4:inst1|q1[1]~151'
        Info: 3: + IC(0.398 ns) + CELL(0.206 ns) = 3.312 ns; Loc. = LCCOMB_X1_Y8_N26; Fanout = 1; COMB Node = 'cnt4:inst1|q1[3]~152'
        Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 3.420 ns; Loc. = LCFF_X1_Y8_N27; Fanout = 8; REG Node = 'cnt4:inst1|q1[3]'
        Info: Total cell delay = 1.993 ns ( 58.27 % )
        Info: Total interconnect delay = 1.427 ns ( 41.73 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.785 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.890 ns) + CELL(0.666 ns) = 2.785 ns; Loc. = LCFF_X1_Y8_N27; Fanout = 8; REG Node = 'cnt4:inst1|q1[3]'
        Info: Total cell delay = 1.756 ns ( 63.05 % )
        Info: Total interconnect delay = 1.029 ns ( 36.95 % )
Info: tco from clock "clk" to destination pin "y[5]" through register "cnt4:inst1|q1[0]" is 8.993 ns
    Info: + Longest clock path from clock "clk" to source register is 2.785 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.890 ns) + CELL(0.666 ns) = 2.785 ns; Loc. = LCFF_X1_Y8_N19; Fanout = 11; REG Node = 'cnt4:inst1|q1[0]'
        Info: Total cell delay = 1.756 ns ( 63.05 % )
        Info: Total interconnect delay = 1.029 ns ( 36.95 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 5.904 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y8_N19; Fanout = 11; REG Node = 'cnt4:inst1|q1[0]'
        Info: 2: + IC(0.814 ns) + CELL(0.370 ns) = 1.184 ns; Loc. = LCCOMB_X1_Y8_N4; Fanout = 1; COMB Node = 'bcd_decoder:inst|Mux2~29'
        Info: 3: + IC(1.490 ns) + CELL(3.230 ns) = 5.904 ns; Loc. = PIN_31; Fanout = 0; PIN Node = 'y[5]'
        Info: Total cell delay = 3.600 ns ( 60.98 % )
        Info: Total interconnect delay = 2.304 ns ( 39.02 % )
Info: th for register "cnt4:inst1|q1[0]" (data pin = "en", clock pin = "clk") is 0.664 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.785 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.890 ns) + CELL(0.666 ns) = 2.785 ns; Loc. = LCFF_X1_Y8_N19; Fanout = 11; REG Node = 'cnt4:inst1|q1[0]'
        Info: Total cell delay = 1.756 ns ( 63.05 % )
        Info: Total interconnect delay = 1.029 ns ( 36.95 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 2.427 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 5; PIN Node = 'en'
        Info: 2: + IC(1.023 ns) + CELL(0.206 ns) = 2.319 ns; Loc. = LCCOMB_X1_Y8_N18; Fanout = 1; COMB Node = 'cnt4:inst1|q1[0]~148'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.427 ns; Loc. = LCFF_X1_Y8_N19; Fanout = 11; REG Node = 'cnt4:inst1|q1[0]'
        Info: Total cell delay = 1.404 ns ( 57.85 % )
        Info: Total interconnect delay = 1.023 ns ( 42.15 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 103 megabytes of memory during processing
    Info: Processing ended: Fri May 18 22:41:57 2007
    Info: Elapsed time: 00:00:08