bcd_decoder.vhd

大量VHDL写的数字系统设计有用实例达到

library ieee;
use ieee.std_logic_1164.all;
entity bcd_decoder is
port(i:in std_logic_vector(3 downto 0);
     y:out std_logic_vector(7 downto 0));
end;
architecture one of bcd_decoder is
begin
process(i)
begin
  case i is
	when"0000"=>y<="11111100";
	when"0001"=>y<="01100000";
	when"0010"=>y<="11011010";
	when"0011"=>y<="11110010";
	when"0100"=>y<="01100110";
	when"0101"=>y<="10110110";
	when"0110"=>y<="10111110";
	when"0111"=>y<="11100000";
	when"1000"=>y<="11111110";
	when"1001"=>y<="11110110";
	when"1010"=>y<="11101110";
	when"1011"=>y<="00111110";
	when"1100"=>y<="10011100";
	when"1101"=>y<="01111010";
	when"1110"=>y<="10011110";
	when"1111"=>y<="10001110";
	when others=>y<="11111111";
  end case;
end process;
end;