📄 d_reg.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register q_temp\[3\] q_temp\[2\] 340.02 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 340.02 MHz between source register \"q_temp\[3\]\" and destination register \"q_temp\[2\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.941 ns " "Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.058 ns + Longest register register " "Info: + Longest register to register delay is 1.058 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q_temp\[3\] 1 REG LCFF_X2_Y1_N17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y1_N17; Fanout = 2; REG Node = 'q_temp\[3\]'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { q_temp[3] } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.744 ns) + CELL(0.206 ns) 0.950 ns q_temp~100 2 COMB LCCOMB_X2_Y1_N24 1 " "Info: 2: + IC(0.744 ns) + CELL(0.206 ns) = 0.950 ns; Loc. = LCCOMB_X2_Y1_N24; Fanout = 1; COMB Node = 'q_temp~100'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.950 ns" { q_temp[3] q_temp~100 } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.058 ns q_temp\[2\] 3 REG LCFF_X2_Y1_N25 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.058 ns; Loc. = LCFF_X2_Y1_N25; Fanout = 2; REG Node = 'q_temp\[2\]'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { q_temp~100 q_temp[2] } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.314 ns ( 29.68 % ) " "Info: Total cell delay = 0.314 ns ( 29.68 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.744 ns ( 70.32 % ) " "Info: Total interconnect delay = 0.744 ns ( 70.32 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.058 ns" { q_temp[3] q_temp~100 q_temp[2] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "1.058 ns" { q_temp[3] q_temp~100 q_temp[2] } { 0.000ns 0.744ns 0.000ns } { 0.000ns 0.206ns 0.108ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.817 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.817 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.922 ns) + CELL(0.666 ns) 2.817 ns q_temp\[2\] 3 REG LCFF_X2_Y1_N25 2 " "Info: 3: + IC(0.922 ns) + CELL(0.666 ns) = 2.817 ns; Loc. = LCFF_X2_Y1_N25; Fanout = 2; REG Node = 'q_temp\[2\]'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.588 ns" { clk~clkctrl q_temp[2] } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.34 % ) " "Info: Total cell delay = 1.756 ns ( 62.34 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.061 ns ( 37.66 % ) " "Info: Total interconnect delay = 1.061 ns ( 37.66 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.817 ns" { clk clk~clkctrl q_temp[2] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.817 ns" { clk clk~combout clk~clkctrl q_temp[2] } { 0.000ns 0.000ns 0.139ns 0.922ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.817 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.817 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.922 ns) + CELL(0.666 ns) 2.817 ns q_temp\[3\] 3 REG LCFF_X2_Y1_N17 2 " "Info: 3: + IC(0.922 ns) + CELL(0.666 ns) = 2.817 ns; Loc. = LCFF_X2_Y1_N17; Fanout = 2; REG Node = 'q_temp\[3\]'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.588 ns" { clk~clkctrl q_temp[3] } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.34 % ) " "Info: Total cell delay = 1.756 ns ( 62.34 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.061 ns ( 37.66 % ) " "Info: Total interconnect delay = 1.061 ns ( 37.66 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.817 ns" { clk clk~clkctrl q_temp[3] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.817 ns" { clk clk~combout clk~clkctrl q_temp[3] } { 0.000ns 0.000ns 0.139ns 0.922ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.817 ns" { clk clk~clkctrl q_temp[2] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.817 ns" { clk clk~combout clk~clkctrl q_temp[2] } { 0.000ns 0.000ns 0.139ns 0.922ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.817 ns" { clk clk~clkctrl q_temp[3] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.817 ns" { clk clk~combout clk~clkctrl q_temp[3] } { 0.000ns 0.000ns 0.139ns 0.922ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 16 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 16 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.058 ns" { q_temp[3] q_temp~100 q_temp[2] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "1.058 ns" { q_temp[3] q_temp~100 q_temp[2] } { 0.000ns 0.744ns 0.000ns } { 0.000ns 0.206ns 0.108ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.817 ns" { clk clk~clkctrl q_temp[2] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.817 ns" { clk clk~combout clk~clkctrl q_temp[2] } { 0.000ns 0.000ns 0.139ns 0.922ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.817 ns" { clk clk~clkctrl q_temp[3] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.817 ns" { clk clk~combout clk~clkctrl q_temp[3] } { 0.000ns 0.000ns 0.139ns 0.922ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { q_temp[2] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { q_temp[2] } { } { } } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 16 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "q_temp\[7\] left_right clk 4.656 ns register " "Info: tsu for register \"q_temp\[7\]\" (data pin = \"left_right\", clock pin = \"clk\") is 4.656 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.513 ns + Longest pin register " "Info: + Longest pin to register delay is 7.513 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns left_right 1 PIN PIN_45 8 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_45; Fanout = 8; PIN Node = 'left_right'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { left_right } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.811 ns) + CELL(0.650 ns) 7.405 ns q_temp~97 2 COMB LCCOMB_X2_Y1_N26 1 " "Info: 2: + IC(5.811 ns) + CELL(0.650 ns) = 7.405 ns; Loc. = LCCOMB_X2_Y1_N26; Fanout = 1; COMB Node = 'q_temp~97'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "6.461 ns" { left_right q_temp~97 } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.513 ns q_temp\[7\] 3 REG LCFF_X2_Y1_N27 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.513 ns; Loc. = LCFF_X2_Y1_N27; Fanout = 2; REG Node = 'q_temp\[7\]'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { q_temp~97 q_temp[7] } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.702 ns ( 22.65 % ) " "Info: Total cell delay = 1.702 ns ( 22.65 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.811 ns ( 77.35 % ) " "Info: Total interconnect delay = 5.811 ns ( 77.35 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "7.513 ns" { left_right q_temp~97 q_temp[7] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "7.513 ns" { left_right left_right~combout q_temp~97 q_temp[7] } { 0.000ns 0.000ns 5.811ns 0.000ns } { 0.000ns 0.944ns 0.650ns 0.108ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 16 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.817 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.817 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.922 ns) + CELL(0.666 ns) 2.817 ns q_temp\[7\] 3 REG LCFF_X2_Y1_N27 2 " "Info: 3: + IC(0.922 ns) + CELL(0.666 ns) = 2.817 ns; Loc. = LCFF_X2_Y1_N27; Fanout = 2; REG Node = 'q_temp\[7\]'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.588 ns" { clk~clkctrl q_temp[7] } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.34 % ) " "Info: Total cell delay = 1.756 ns ( 62.34 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.061 ns ( 37.66 % ) " "Info: Total interconnect delay = 1.061 ns ( 37.66 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.817 ns" { clk clk~clkctrl q_temp[7] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.817 ns" { clk clk~combout clk~clkctrl q_temp[7] } { 0.000ns 0.000ns 0.139ns 0.922ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "7.513 ns" { left_right q_temp~97 q_temp[7] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "7.513 ns" { left_right left_right~combout q_temp~97 q_temp[7] } { 0.000ns 0.000ns 5.811ns 0.000ns } { 0.000ns 0.944ns 0.650ns 0.108ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.817 ns" { clk clk~clkctrl q_temp[7] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.817 ns" { clk clk~combout clk~clkctrl q_temp[7] } { 0.000ns 0.000ns 0.139ns 0.922ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout_r q_temp\[0\] 7.620 ns register " "Info: tco from clock \"clk\" to destination pin \"dout_r\" through register \"q_temp\[0\]\" is 7.620 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.817 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.817 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.922 ns) + CELL(0.666 ns) 2.817 ns q_temp\[0\] 3 REG LCFF_X2_Y1_N31 2 " "Info: 3: + IC(0.922 ns) + CELL(0.666 ns) = 2.817 ns; Loc. = LCFF_X2_Y1_N31; Fanout = 2; REG Node = 'q_temp\[0\]'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.588 ns" { clk~clkctrl q_temp[0] } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.34 % ) " "Info: Total cell delay = 1.756 ns ( 62.34 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.061 ns ( 37.66 % ) " "Info: Total interconnect delay = 1.061 ns ( 37.66 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.817 ns" { clk clk~clkctrl q_temp[0] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.817 ns" { clk clk~combout clk~clkctrl q_temp[0] } { 0.000ns 0.000ns 0.139ns 0.922ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 16 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.499 ns + Longest register pin " "Info: + Longest register to pin delay is 4.499 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q_temp\[0\] 1 REG LCFF_X2_Y1_N31 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y1_N31; Fanout = 2; REG Node = 'q_temp\[0\]'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { q_temp[0] } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.443 ns) + CELL(3.056 ns) 4.499 ns dout_r 2 PIN PIN_30 0 " "Info: 2: + IC(1.443 ns) + CELL(3.056 ns) = 4.499 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'dout_r'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "4.499 ns" { q_temp[0] dout_r } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.056 ns ( 67.93 % ) " "Info: Total cell delay = 3.056 ns ( 67.93 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.443 ns ( 32.07 % ) " "Info: Total interconnect delay = 1.443 ns ( 32.07 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "4.499 ns" { q_temp[0] dout_r } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "4.499 ns" { q_temp[0] dout_r } { 0.000ns 1.443ns } { 0.000ns 3.056ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.817 ns" { clk clk~clkctrl q_temp[0] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.817 ns" { clk clk~combout clk~clkctrl q_temp[0] } { 0.000ns 0.000ns 0.139ns 0.922ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "4.499 ns" { q_temp[0] dout_r } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "4.499 ns" { q_temp[0] dout_r } { 0.000ns 1.443ns } { 0.000ns 3.056ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "q_temp\[7\] din clk -4.279 ns register " "Info: th for register \"q_temp\[7\]\" (data pin = \"din\", clock pin = \"clk\") is -4.279 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.817 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.817 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.922 ns) + CELL(0.666 ns) 2.817 ns q_temp\[7\] 3 REG LCFF_X2_Y1_N27 2 " "Info: 3: + IC(0.922 ns) + CELL(0.666 ns) = 2.817 ns; Loc. = LCFF_X2_Y1_N27; Fanout = 2; REG Node = 'q_temp\[7\]'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.588 ns" { clk~clkctrl q_temp[7] } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.34 % ) " "Info: Total cell delay = 1.756 ns ( 62.34 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.061 ns ( 37.66 % ) " "Info: Total interconnect delay = 1.061 ns ( 37.66 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.817 ns" { clk clk~clkctrl q_temp[7] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.817 ns" { clk clk~combout clk~clkctrl q_temp[7] } { 0.000ns 0.000ns 0.139ns 0.922ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" { } { { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 16 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.402 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.402 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns din 1 PIN PIN_43 2 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_43; Fanout = 2; PIN Node = 'din'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { din } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.726 ns) + CELL(0.624 ns) 7.294 ns q_temp~97 2 COMB LCCOMB_X2_Y1_N26 1 " "Info: 2: + IC(5.726 ns) + CELL(0.624 ns) = 7.294 ns; Loc. = LCCOMB_X2_Y1_N26; Fanout = 1; COMB Node = 'q_temp~97'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "6.350 ns" { din q_temp~97 } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.402 ns q_temp\[7\] 3 REG LCFF_X2_Y1_N27 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.402 ns; Loc. = LCFF_X2_Y1_N27; Fanout = 2; REG Node = 'q_temp\[7\]'" { } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { q_temp~97 q_temp[7] } "NODE_NAME" } } { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.676 ns ( 22.64 % ) " "Info: Total cell delay = 1.676 ns ( 22.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.726 ns ( 77.36 % ) " "Info: Total interconnect delay = 5.726 ns ( 77.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "7.402 ns" { din q_temp~97 q_temp[7] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "7.402 ns" { din din~combout q_temp~97 q_temp[7] } { 0.000ns 0.000ns 5.726ns 0.000ns } { 0.000ns 0.944ns 0.624ns 0.108ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.817 ns" { clk clk~clkctrl q_temp[7] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.817 ns" { clk clk~combout clk~clkctrl q_temp[7] } { 0.000ns 0.000ns 0.139ns 0.922ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "7.402 ns" { din q_temp~97 q_temp[7] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "7.402 ns" { din din~combout q_temp~97 q_temp[7] } { 0.000ns 0.000ns 5.726ns 0.000ns } { 0.000ns 0.944ns 0.624ns 0.108ns } } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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