d_reg.map.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 18 22:18:26 2007 " "Info: Processing started: Sun Mar 18 22:18:26 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off d_reg -c d_reg " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off d_reg -c d_reg" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"else\";  expecting \";\" d_reg.vhd(22) " "Error (10500): VHDL syntax error at d_reg.vhd(22) near text \"else\";  expecting \";\"" {  } { { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 22 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"end\";  expecting \";\" d_reg.vhd(27) " "Error (10500): VHDL syntax error at d_reg.vhd(27) near text \"end\";  expecting \";\"" {  } { { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 27 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"process\";  expecting \"if\" d_reg.vhd(29) " "Error (10500): VHDL syntax error at d_reg.vhd(29) near text \"process\";  expecting \"if\"" {  } { { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 29 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\";\";  expecting \"if\" d_reg.vhd(32) " "Error (10500): VHDL syntax error at d_reg.vhd(32) near text \";\";  expecting \"if\"" {  } { { "d_reg.vhd" "" { Text "D:/my_eda/d_reg/d_reg.vhd" 32 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d_reg.vhd 0 0 " "Info: Found 0 design units, including 0 entities, in source file d_reg.vhd" {  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 4 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 4 errors, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Sun Mar 18 22:18:29 2007 " "Error: Processing ended: Sun Mar 18 22:18:29 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:05 " "Error: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}