d_reg.tan.rpt

大量VHDL写的数字系统设计有用实例达到

; N/A   ; None         ; 4.624 ns   ; left_right ; q_temp[6] ; clk      ;
; N/A   ; None         ; 4.623 ns   ; left_right ; q_temp[4] ; clk      ;
; N/A   ; None         ; 4.621 ns   ; left_right ; q_temp[2] ; clk      ;
; N/A   ; None         ; 4.614 ns   ; left_right ; q_temp[5] ; clk      ;
; N/A   ; None         ; 4.546 ns   ; din        ; q_temp[0] ; clk      ;
; N/A   ; None         ; 4.545 ns   ; din        ; q_temp[7] ; clk      ;
+-------+--------------+------------+------------+-----------+----------+


+---------------------------------------------------------------------+
; tco                                                                 ;
+-------+--------------+------------+-----------+--------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To     ; From Clock ;
+-------+--------------+------------+-----------+--------+------------+
; N/A   ; None         ; 7.620 ns   ; q_temp[0] ; dout_r ; clk        ;
; N/A   ; None         ; 7.277 ns   ; q_temp[7] ; dout_l ; clk        ;
+-------+--------------+------------+-----------+--------+------------+


+-----------------------------------------------------------------------------+
; th                                                                          ;
+---------------+-------------+-----------+------------+-----------+----------+
; Minimum Slack ; Required th ; Actual th ; From       ; To        ; To Clock ;
+---------------+-------------+-----------+------------+-----------+----------+
; N/A           ; None        ; -4.279 ns ; din        ; q_temp[7] ; clk      ;
; N/A           ; None        ; -4.280 ns ; din        ; q_temp[0] ; clk      ;
; N/A           ; None        ; -4.348 ns ; left_right ; q_temp[5] ; clk      ;
; N/A           ; None        ; -4.355 ns ; left_right ; q_temp[2] ; clk      ;
; N/A           ; None        ; -4.357 ns ; left_right ; q_temp[4] ; clk      ;
; N/A           ; None        ; -4.358 ns ; left_right ; q_temp[3] ; clk      ;
; N/A           ; None        ; -4.358 ns ; left_right ; q_temp[6] ; clk      ;
; N/A           ; None        ; -4.382 ns ; left_right ; q_temp[1] ; clk      ;
; N/A           ; None        ; -4.389 ns ; left_right ; q_temp[0] ; clk      ;
; N/A           ; None        ; -4.390 ns ; left_right ; q_temp[7] ; clk      ;
+---------------+-------------+-----------+------------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Sun Mar 18 22:06:47 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off d_reg -c d_reg --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 340.02 MHz between source register "q_temp[3]" and destination register "q_temp[2]"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.058 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y1_N17; Fanout = 2; REG Node = 'q_temp[3]'
            Info: 2: + IC(0.744 ns) + CELL(0.206 ns) = 0.950 ns; Loc. = LCCOMB_X2_Y1_N24; Fanout = 1; COMB Node = 'q_temp~100'
            Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.058 ns; Loc. = LCFF_X2_Y1_N25; Fanout = 2; REG Node = 'q_temp[2]'
            Info: Total cell delay = 0.314 ns ( 29.68 % )
            Info: Total interconnect delay = 0.744 ns ( 70.32 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.817 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.922 ns) + CELL(0.666 ns) = 2.817 ns; Loc. = LCFF_X2_Y1_N25; Fanout = 2; REG Node = 'q_temp[2]'
                Info: Total cell delay = 1.756 ns ( 62.34 % )
                Info: Total interconnect delay = 1.061 ns ( 37.66 % )
            Info: - Longest clock path from clock "clk" to source register is 2.817 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.922 ns) + CELL(0.666 ns) = 2.817 ns; Loc. = LCFF_X2_Y1_N17; Fanout = 2; REG Node = 'q_temp[3]'
                Info: Total cell delay = 1.756 ns ( 62.34 % )
                Info: Total interconnect delay = 1.061 ns ( 37.66 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "q_temp[7]" (data pin = "left_right", clock pin = "clk") is 4.656 ns
    Info: + Longest pin to register delay is 7.513 ns
        Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_45; Fanout = 8; PIN Node = 'left_right'
        Info: 2: + IC(5.811 ns) + CELL(0.650 ns) = 7.405 ns; Loc. = LCCOMB_X2_Y1_N26; Fanout = 1; COMB Node = 'q_temp~97'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.513 ns; Loc. = LCFF_X2_Y1_N27; Fanout = 2; REG Node = 'q_temp[7]'
        Info: Total cell delay = 1.702 ns ( 22.65 % )
        Info: Total interconnect delay = 5.811 ns ( 77.35 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.817 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.922 ns) + CELL(0.666 ns) = 2.817 ns; Loc. = LCFF_X2_Y1_N27; Fanout = 2; REG Node = 'q_temp[7]'
        Info: Total cell delay = 1.756 ns ( 62.34 % )
        Info: Total interconnect delay = 1.061 ns ( 37.66 % )
Info: tco from clock "clk" to destination pin "dout_r" through register "q_temp[0]" is 7.620 ns
    Info: + Longest clock path from clock "clk" to source register is 2.817 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.922 ns) + CELL(0.666 ns) = 2.817 ns; Loc. = LCFF_X2_Y1_N31; Fanout = 2; REG Node = 'q_temp[0]'
        Info: Total cell delay = 1.756 ns ( 62.34 % )
        Info: Total interconnect delay = 1.061 ns ( 37.66 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 4.499 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y1_N31; Fanout = 2; REG Node = 'q_temp[0]'
        Info: 2: + IC(1.443 ns) + CELL(3.056 ns) = 4.499 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'dout_r'
        Info: Total cell delay = 3.056 ns ( 67.93 % )
        Info: Total interconnect delay = 1.443 ns ( 32.07 % )
Info: th for register "q_temp[7]" (data pin = "din", clock pin = "clk") is -4.279 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.817 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.922 ns) + CELL(0.666 ns) = 2.817 ns; Loc. = LCFF_X2_Y1_N27; Fanout = 2; REG Node = 'q_temp[7]'
        Info: Total cell delay = 1.756 ns ( 62.34 % )
        Info: Total interconnect delay = 1.061 ns ( 37.66 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 7.402 ns
        Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_43; Fanout = 2; PIN Node = 'din'
        Info: 2: + IC(5.726 ns) + CELL(0.624 ns) = 7.294 ns; Loc. = LCCOMB_X2_Y1_N26; Fanout = 1; COMB Node = 'q_temp~97'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.402 ns; Loc. = LCFF_X2_Y1_N27; Fanout = 2; REG Node = 'q_temp[7]'
        Info: Total cell delay = 1.676 ns ( 22.64 % )
        Info: Total interconnect delay = 5.726 ns ( 77.36 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Mar 18 22:06:47 2007
    Info: Elapsed time: 00:00:02