📄 reg8_1.tan.rpt
字号:
Timing Analyzer report for reg8_1
Fri Mar 16 15:47:31 2007
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. tsu
6. tco
7. th
8. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+--------------+-----------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+--------------+-----------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 4.267 ns ; d[1] ; q_temp[1] ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 10.546 ns ; q_temp[0]~en ; q[1] ; clk ; -- ; 0 ;
; Worst-case th ; N/A ; None ; 0.695 ns ; d[7] ; q_temp[7] ; -- ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+--------------+-----------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C8T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+-----------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+------+-----------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+-----------+----------+
; N/A ; None ; 4.267 ns ; d[1] ; q_temp[1] ; clk ;
; N/A ; None ; 4.111 ns ; d[2] ; q_temp[2] ; clk ;
; N/A ; None ; 3.650 ns ; d[3] ; q_temp[3] ; clk ;
; N/A ; None ; 3.573 ns ; d[0] ; q_temp[0] ; clk ;
; N/A ; None ; 0.259 ns ; d[5] ; q_temp[5] ; clk ;
; N/A ; None ; 0.085 ns ; d[4] ; q_temp[4] ; clk ;
; N/A ; None ; -0.089 ns ; d[6] ; q_temp[6] ; clk ;
; N/A ; None ; -0.429 ns ; d[7] ; q_temp[7] ; clk ;
+-------+--------------+------------+------+-----------+----------+
+----------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+--------------+------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+--------------+------+------------+
; N/A ; None ; 10.546 ns ; q_temp[0]~en ; q[1] ; clk ;
; N/A ; None ; 10.094 ns ; q_temp[0]~en ; q[5] ; clk ;
; N/A ; None ; 10.033 ns ; q_temp[0]~en ; q[0] ; clk ;
; N/A ; None ; 9.989 ns ; q_temp[0]~en ; q[7] ; clk ;
; N/A ; None ; 9.979 ns ; q_temp[0]~en ; q[3] ; clk ;
; N/A ; None ; 9.977 ns ; q_temp[0]~en ; q[6] ; clk ;
; N/A ; None ; 9.968 ns ; q_temp[0]~en ; q[4] ; clk ;
; N/A ; None ; 8.550 ns ; q_temp[0]~en ; q[2] ; clk ;
; N/A ; None ; 8.107 ns ; q_temp[7] ; q[7] ; clk ;
; N/A ; None ; 8.100 ns ; q_temp[5] ; q[5] ; clk ;
; N/A ; None ; 8.096 ns ; q_temp[6] ; q[6] ; clk ;
; N/A ; None ; 8.062 ns ; q_temp[4] ; q[4] ; clk ;
; N/A ; None ; 7.272 ns ; q_temp[3] ; q[3] ; clk ;
; N/A ; None ; 7.158 ns ; q_temp[2] ; q[2] ; clk ;
; N/A ; None ; 7.012 ns ; q_temp[1] ; q[1] ; clk ;
; N/A ; None ; 6.880 ns ; q_temp[0] ; q[0] ; clk ;
+-------+--------------+------------+--------------+------+------------+
+-----------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+------+-----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+------+-----------+----------+
; N/A ; None ; 0.695 ns ; d[7] ; q_temp[7] ; clk ;
; N/A ; None ; 0.355 ns ; d[6] ; q_temp[6] ; clk ;
; N/A ; None ; 0.181 ns ; d[4] ; q_temp[4] ; clk ;
; N/A ; None ; 0.007 ns ; d[5] ; q_temp[5] ; clk ;
; N/A ; None ; -3.307 ns ; d[0] ; q_temp[0] ; clk ;
; N/A ; None ; -3.384 ns ; d[3] ; q_temp[3] ; clk ;
; N/A ; None ; -3.845 ns ; d[2] ; q_temp[2] ; clk ;
; N/A ; None ; -4.001 ns ; d[1] ; q_temp[1] ; clk ;
+---------------+-------------+-----------+------+-----------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
Info: Processing started: Fri Mar 16 15:47:31 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off reg8_1 -c reg8_1 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: No valid register-to-register data paths exist for clock "clk"
Info: tsu for register "q_temp[1]" (data pin = "d[1]", clock pin = "clk") is 4.267 ns
Info: + Longest pin to register delay is 7.131 ns
Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_113; Fanout = 1; PIN Node = 'd[1]'
Info: 2: + IC(5.727 ns) + CELL(0.460 ns) = 7.131 ns; Loc. = LCFF_X33_Y17_N7; Fanout = 1; REG Node = 'q_temp[1]'
Info: Total cell delay = 1.404 ns ( 19.69 % )
Info: Total interconnect delay = 5.727 ns ( 80.31 % )
Info: + Micro setup delay of destination is -0.040 ns
Info: - Shortest clock path from clock "clk" to destination register is 2.824 ns
Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 9; COMB Node = 'clk~clkctrl'
Info: 3: + IC(0.929 ns) + CELL(0.666 ns) = 2.824 ns; Loc. = LCFF_X33_Y17_N7; Fanout = 1; REG Node = 'q_temp[1]'
Info: Total cell delay = 1.756 ns ( 62.18 % )
Info: Total interconnect delay = 1.068 ns ( 37.82 % )
Info: tco from clock "clk" to destination pin "q[1]" through register "q_temp[0]~en" is 10.546 ns
Info: + Longest clock path from clock "clk" to source register is 2.815 ns
Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 9; COMB Node = 'clk~clkctrl'
Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.815 ns; Loc. = LCFF_X25_Y17_N9; Fanout = 8; REG Node = 'q_temp[0]~en'
Info: Total cell delay = 1.756 ns ( 62.38 % )
Info: Total interconnect delay = 1.059 ns ( 37.62 % )
Info: + Micro clock to output delay of source is 0.304 ns
Info: + Longest register to pin delay is 7.427 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y17_N9; Fanout = 8; REG Node = 'q_temp[0]~en'
Info: 2: + IC(4.342 ns) + CELL(3.085 ns) = 7.427 ns; Loc. = PIN_104; Fanout = 0; PIN Node = 'q[1]'
Info: Total cell delay = 3.085 ns ( 41.54 % )
Info: Total interconnect delay = 4.342 ns ( 58.46 % )
Info: th for register "q_temp[7]" (data pin = "d[7]", clock pin = "clk") is 0.695 ns
Info: + Longest clock path from clock "clk" to destination register is 2.777 ns
Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 9; COMB Node = 'clk~clkctrl'
Info: 3: + IC(0.882 ns) + CELL(0.666 ns) = 2.777 ns; Loc. = LCFF_X33_Y9_N21; Fanout = 1; REG Node = 'q_temp[7]'
Info: Total cell delay = 1.756 ns ( 63.23 % )
Info: Total interconnect delay = 1.021 ns ( 36.77 % )
Info: + Micro hold delay of destination is 0.306 ns
Info: - Shortest pin to register delay is 2.388 ns
Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_91; Fanout = 1; PIN Node = 'd[7]'
Info: 2: + IC(0.974 ns) + CELL(0.206 ns) = 2.280 ns; Loc. = LCCOMB_X33_Y9_N20; Fanout = 1; COMB Node = 'q_temp[7]~feeder'
Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.388 ns; Loc. = LCFF_X33_Y9_N21; Fanout = 1; REG Node = 'q_temp[7]'
Info: Total cell delay = 1.414 ns ( 59.21 % )
Info: Total interconnect delay = 0.974 ns ( 40.79 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Fri Mar 16 15:47:31 2007
Info: Elapsed time: 00:00:02
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