reg8_1.tan.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Info" "ITDB_TSU_RESULT" "q_temp\[1\] d\[1\] clk 4.267 ns register " "Info: tsu for register \"q_temp\[1\]\" (data pin = \"d\[1\]\", clock pin = \"clk\") is 4.267 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.131 ns + Longest pin register " "Info: + Longest pin to register delay is 7.131 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns d\[1\] 1 PIN PIN_113 1 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_113; Fanout = 1; PIN Node = 'd\[1\]'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { d[1] } "NODE_NAME" } } { "reg8_1.vhd" "" { Text "D:/my_eda/reg8_1/reg8_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.727 ns) + CELL(0.460 ns) 7.131 ns q_temp\[1\] 2 REG LCFF_X33_Y17_N7 1 " "Info: 2: + IC(5.727 ns) + CELL(0.460 ns) = 7.131 ns; Loc. = LCFF_X33_Y17_N7; Fanout = 1; REG Node = 'q_temp\[1\]'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "6.187 ns" { d[1] q_temp[1] } "NODE_NAME" } } { "reg8_1.vhd" "" { Text "D:/my_eda/reg8_1/reg8_1.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.404 ns ( 19.69 % ) " "Info: Total cell delay = 1.404 ns ( 19.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.727 ns ( 80.31 % ) " "Info: Total interconnect delay = 5.727 ns ( 80.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "7.131 ns" { d[1] q_temp[1] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "7.131 ns" { d[1] d[1]~combout q_temp[1] } { 0.000ns 0.000ns 5.727ns } { 0.000ns 0.944ns 0.460ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "reg8_1.vhd" "" { Text "D:/my_eda/reg8_1/reg8_1.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.824 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.824 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "reg8_1.vhd" "" { Text "D:/my_eda/reg8_1/reg8_1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 9 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 9; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "reg8_1.vhd" "" { Text "D:/my_eda/reg8_1/reg8_1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.666 ns) 2.824 ns q_temp\[1\] 3 REG LCFF_X33_Y17_N7 1 " "Info: 3: + IC(0.929 ns) + CELL(0.666 ns) = 2.824 ns; Loc. = LCFF_X33_Y17_N7; Fanout = 1; REG Node = 'q_temp\[1\]'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.595 ns" { clk~clkctrl q_temp[1] } "NODE_NAME" } } { "reg8_1.vhd" "" { Text "D:/my_eda/reg8_1/reg8_1.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.18 % ) " "Info: Total cell delay = 1.756 ns ( 62.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.068 ns ( 37.82 % ) " "Info: Total interconnect delay = 1.068 ns ( 37.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.824 ns" { clk clk~clkctrl q_temp[1] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.824 ns" { clk clk~combout clk~clkctrl q_temp[1] } { 0.000ns 0.000ns 0.139ns 0.929ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "7.131 ns" { d[1] q_temp[1] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "7.131 ns" { d[1] d[1]~combout q_temp[1] } { 0.000ns 0.000ns 5.727ns } { 0.000ns 0.944ns 0.460ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.824 ns" { clk clk~clkctrl q_temp[1] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.824 ns" { clk clk~combout clk~clkctrl q_temp[1] } { 0.000ns 0.000ns 0.139ns 0.929ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[1\] q_temp\[0\]~en 10.546 ns register " "Info: tco from clock \"clk\" to destination pin \"q\[1\]\" through register \"q_temp\[0\]~en\" is 10.546 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.815 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.815 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "reg8_1.vhd" "" { Text "D:/my_eda/reg8_1/reg8_1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 9 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 9; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "reg8_1.vhd" "" { Text "D:/my_eda/reg8_1/reg8_1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.920 ns) + CELL(0.666 ns) 2.815 ns q_temp\[0\]~en 3 REG LCFF_X25_Y17_N9 8 " "Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.815 ns; Loc. = LCFF_X25_Y17_N9; Fanout = 8; REG Node = 'q_temp\[0\]~en'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.586 ns" { clk~clkctrl q_temp[0]~en } "NODE_NAME" } } { "reg8_1.vhd" "" { Text "D:/my_eda/reg8_1/reg8_1.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.38 % ) " "Info: Total cell delay = 1.756 ns ( 62.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.059 ns ( 37.62 % ) " "Info: Total interconnect delay = 1.059 ns ( 37.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.815 ns" { clk clk~clkctrl q_temp[0]~en } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.815 ns" { clk clk~combout clk~clkctrl q_temp[0]~en } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "reg8_1.vhd" "" { Text "D:/my_eda/reg8_1/reg8_1.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.427 ns + Longest register pin " "Info: + Longest register to pin delay is 7.427 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q_temp\[0\]~en 1 REG LCFF_X25_Y17_N9 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y17_N9; Fanout = 8; REG Node = 'q_temp\[0\]~en'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { q_temp[0]~en } "NODE_NAME" } } { "reg8_1.vhd" "" { Text "D:/my_eda/reg8_1/reg8_1.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.342 ns) + CELL(3.085 ns) 7.427 ns q\[1\] 2 PIN PIN_104 0 " "Info: 2: + IC(4.342 ns) + CELL(3.085 ns) = 7.427 ns; Loc. = PIN_104; Fanout = 0; PIN Node = 'q\[1\]'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "7.427 ns" { q_temp[0]~en q[1] } "NODE_NAME" } } { "reg8_1.vhd" "" { Text "D:/my_eda/reg8_1/reg8_1.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.085 ns ( 41.54 % ) " "Info: Total cell delay = 3.085 ns ( 41.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.342 ns ( 58.46 % ) " "Info: Total interconnect delay = 4.342 ns ( 58.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "7.427 ns" { q_temp[0]~en q[1] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "7.427 ns" { q_temp[0]~en q[1] } { 0.000ns 4.342ns } { 0.000ns 3.085ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.815 ns" { clk clk~clkctrl q_temp[0]~en } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.815 ns" { clk clk~combout clk~clkctrl q_temp[0]~en } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "7.427 ns" { q_temp[0]~en q[1] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "7.427 ns" { q_temp[0]~en q[1] } { 0.000ns 4.342ns } { 0.000ns 3.085ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "q_temp\[7\] d\[7\] clk 0.695 ns register " "Info: th for register \"q_temp\[7\]\" (data pin = \"d\[7\]\", clock pin = \"clk\") is 0.695 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.777 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.777 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "reg8_1.vhd" "" { Text "D:/my_eda/reg8_1/reg8_1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 9 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 9; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "reg8_1.vhd" "" { Text "D:/my_eda/reg8_1/reg8_1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.882 ns) + CELL(0.666 ns) 2.777 ns q_temp\[7\] 3 REG LCFF_X33_Y9_N21 1 " "Info: 3: + IC(0.882 ns) + CELL(0.666 ns) = 2.777 ns; Loc. = LCFF_X33_Y9_N21; Fanout = 1; REG Node = 'q_temp\[7\]'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.548 ns" { clk~clkctrl q_temp[7] } "NODE_NAME" } } { "reg8_1.vhd" "" { Text "D:/my_eda/reg8_1/reg8_1.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.23 % ) " "Info: Total cell delay = 1.756 ns ( 63.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.021 ns ( 36.77 % ) " "Info: Total interconnect delay = 1.021 ns ( 36.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.777 ns" { clk clk~clkctrl q_temp[7] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.777 ns" { clk clk~combout clk~clkctrl q_temp[7] } { 0.000ns 0.000ns 0.139ns 0.882ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "reg8_1.vhd" "" { Text "D:/my_eda/reg8_1/reg8_1.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.388 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.388 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns d\[7\] 1 PIN PIN_91 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_91; Fanout = 1; PIN Node = 'd\[7\]'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { d[7] } "NODE_NAME" } } { "reg8_1.vhd" "" { Text "D:/my_eda/reg8_1/reg8_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.974 ns) + CELL(0.206 ns) 2.280 ns q_temp\[7\]~feeder 2 COMB LCCOMB_X33_Y9_N20 1 " "Info: 2: + IC(0.974 ns) + CELL(0.206 ns) = 2.280 ns; Loc. = LCCOMB_X33_Y9_N20; Fanout = 1; COMB Node = 'q_temp\[7\]~feeder'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.180 ns" { d[7] q_temp[7]~feeder } "NODE_NAME" } } { "reg8_1.vhd" "" { Text "D:/my_eda/reg8_1/reg8_1.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.388 ns q_temp\[7\] 3 REG LCFF_X33_Y9_N21 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.388 ns; Loc. = LCFF_X33_Y9_N21; Fanout = 1; REG Node = 'q_temp\[7\]'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { q_temp[7]~feeder q_temp[7] } "NODE_NAME" } } { "reg8_1.vhd" "" { Text "D:/my_eda/reg8_1/reg8_1.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.414 ns ( 59.21 % ) " "Info: Total cell delay = 1.414 ns ( 59.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.974 ns ( 40.79 % ) " "Info: Total interconnect delay = 0.974 ns ( 40.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.388 ns" { d[7] q_temp[7]~feeder q_temp[7] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.388 ns" { d[7] d[7]~combout q_temp[7]~feeder q_temp[7] } { 0.000ns 0.000ns 0.974ns 0.000ns } { 0.000ns 1.100ns 0.206ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.777 ns" { clk clk~clkctrl q_temp[7] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.777 ns" { clk clk~combout clk~clkctrl q_temp[7] } { 0.000ns 0.000ns 0.139ns 0.882ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.388 ns" { d[7] q_temp[7]~feeder q_temp[7] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.388 ns" { d[7] d[7]~combout q_temp[7]~feeder q_temp[7] } { 0.000ns 0.000ns 0.974ns 0.000ns } { 0.000ns 1.100ns 0.206ns 0.108ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 16 15:47:31 2007 " "Info: Processing ended: Fri Mar 16 15:47:31 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}