cnt4.vhd

大量VHDL写的数字系统设计有用实例达到

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2007 Altera Corporation
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-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
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-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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-- Generated by Quartus II Version 7.0 (Build Build 33 02/05/2007)
-- Created on Sun May 20 10:32:33 2007

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt4 is
port(clk:in std_logic;
rst:in std_logic;
en:in std_logic;
q:out std_logic_vector(3 downto 0));
end;
architecture one of cnt4 is
signal q1:std_logic_vector(3 downto 0);
begin
Process(clk,en,rst)
begin
if en='1' then
if rst='1' then q1<="0000";
elsif clk'event and clk='1' then 
q1<=q1+1;
end if;
end if;
end process;
q<=q1;
end;
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		clk : IN STD_LOGIC;
		en : IN STD_LOGIC;
		rst : IN STD_LOGIC;
		q : OUT STD_LOGIC_VECTOR(3 downto 0)
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!