bcd_decoder.vhd

大量VHDL写的数字系统设计有用实例达到

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.


-- Generated by Quartus II Version 7.0 (Build Build 33 02/05/2007)
-- Created on Sun May 20 10:48:38 2007

library ieee;
use ieee.std_logic_1164.all;
entity bcd_decoder is
port(i:in std_logic_vector(3 downto 0);
     y:out std_logic_vector(7 downto 0));
end;
architecture one of bcd_decoder is
begin
process(i)
begin
  case i is
	when"0000"=>y<="11111100";
	when"0001"=>y<="01100000";
	when"0010"=>y<="11011010";
	when"0011"=>y<="11110010";
	when"0100"=>y<="01100110";
	when"0101"=>y<="10110110";
	when"0110"=>y<="10111110";
	when"0111"=>y<="11100000";
	when"1000"=>y<="11111110";
	when"1001"=>y<="11110110";
	when"1010"=>y<="11101110";
	when"1011"=>y<="00111110";
	when"1100"=>y<="10011100";
	when"1101"=>y<="01111010";
	when"1110"=>y<="10011110";
	when"1111"=>y<="10001110";
	when others=>y<="11111111";
  end case;
end process;
end;