tri_bibuffer.hier_info

大量VHDL写的数字系统设计有用实例达到

|tri_bibuffer
a[0] <= process1~8
a[1] <= process1~7
a[2] <= process1~6
a[3] <= process1~5
a[4] <= process1~4
a[5] <= process1~3
a[6] <= process1~2
a[7] <= process1~1
b[0] <= process0~8
b[1] <= process0~7
b[2] <= process0~6
b[3] <= process0~5
b[4] <= process0~4
b[5] <= process0~3
b[6] <= process0~2
b[7] <= process0~1
en => process1~0.IN1
en => process0~0.IN1
dr => process0~0.IN0
dr => process1~0.IN0