prev_cmp_tri_bibuffer.fit.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X23_Y0 X34_Y9 " "Info: The peak interconnect region extends from location X23_Y0 to location X34_Y9" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "16 " "Warning: Found 16 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "a\[0\] 0 " "Info: Pin \"a\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "a\[1\] 0 " "Info: Pin \"a\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "a\[2\] 0 " "Info: Pin \"a\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "a\[3\] 0 " "Info: Pin \"a\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "a\[4\] 0 " "Info: Pin \"a\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "a\[5\] 0 " "Info: Pin \"a\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "a\[6\] 0 " "Info: Pin \"a\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "a\[7\] 0 " "Info: Pin \"a\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "b\[0\] 0 " "Info: Pin \"b\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "b\[1\] 0 " "Info: Pin \"b\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "b\[2\] 0 " "Info: Pin \"b\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "b\[3\] 0 " "Info: Pin \"b\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "b\[4\] 0 " "Info: Pin \"b\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "b\[5\] 0 " "Info: Pin \"b\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "b\[6\] 0 " "Info: Pin \"b\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "b\[7\] 0 " "Info: Pin \"b\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IFIOMGR_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "process1~0 " "Info: Following pins have the same output enable: process1~0" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional a\[0\] 3.3-V LVTTL " "Info: Type bidirectional pin a\[0\] uses the 3.3-V LVTTL I/O standard" {  } { { "tri_bibuffer.vhd" "" { Text "D:/my_eda/tri_bibuffer/tri_bibuffer.vhd" 4 -1 0 } } { "e:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "a\[0\]" } } } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[0] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional a\[4\] 3.3-V LVTTL " "Info: Type bidirectional pin a\[4\] uses the 3.3-V LVTTL I/O standard" {  } { { "tri_bibuffer.vhd" "" { Text "D:/my_eda/tri_bibuffer/tri_bibuffer.vhd" 4 -1 0 } } { "e:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "a\[4\]" } } } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[4] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional a\[3\] 3.3-V LVTTL " "Info: Type bidirectional pin a\[3\] uses the 3.3-V LVTTL I/O standard" {  } { { "tri_bibuffer.vhd" "" { Text "D:/my_eda/tri_bibuffer/tri_bibuffer.vhd" 4 -1 0 } } { "e:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "a\[3\]" } } } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[3] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional a\[7\] 3.3-V LVTTL " "Info: Type bidirectional pin a\[7\] uses the 3.3-V LVTTL I/O standard" {  } { { "tri_bibuffer.vhd" "" { Text "D:/my_eda/tri_bibuffer/tri_bibuffer.vhd" 4 -1 0 } } { "e:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "a\[7\]" } } } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[7] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional a\[2\] 3.3-V LVTTL " "Info: Type bidirectional pin a\[2\] uses the 3.3-V LVTTL I/O standard" {  } { { "tri_bibuffer.vhd" "" { Text "D:/my_eda/tri_bibuffer/tri_bibuffer.vhd" 4 -1 0 } } { "e:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "a\[2\]" } } } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[2] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[2] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional a\[6\] 3.3-V LVTTL " "Info: Type bidirectional pin a\[6\] uses the 3.3-V LVTTL I/O standard" {  } { { "tri_bibuffer.vhd" "" { Text "D:/my_eda/tri_bibuffer/tri_bibuffer.vhd" 4 -1 0 } } { "e:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "a\[6\]" } } } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[6] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional a\[1\] 3.3-V LVTTL " "Info: Type bidirectional pin a\[1\] uses the 3.3-V LVTTL I/O standard" {  } { { "tri_bibuffer.vhd" "" { Text "D:/my_eda/tri_bibuffer/tri_bibuffer.vhd" 4 -1 0 } } { "e:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "a\[1\]" } } } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[1] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[1] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional a\[5\] 3.3-V LVTTL " "Info: Type bidirectional pin a\[5\] uses the 3.3-V LVTTL I/O standard" {  } { { "tri_bibuffer.vhd" "" { Text "D:/my_eda/tri_bibuffer/tri_bibuffer.vhd" 4 -1 0 } } { "e:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "a\[5\]" } } } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[5] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "process0~0 " "Info: Following pins have the same output enable: process0~0" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional b\[0\] 3.3-V LVTTL " "Info: Type bidirectional pin b\[0\] uses the 3.3-V LVTTL I/O standard" {  } { { "tri_bibuffer.vhd" "" { Text "D:/my_eda/tri_bibuffer/tri_bibuffer.vhd" 4 -1 0 } } { "e:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "b\[0\]" } } } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { b[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { b[0] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional b\[4\] 3.3-V LVTTL " "Info: Type bidirectional pin b\[4\] uses the 3.3-V LVTTL I/O standard" {  } { { "tri_bibuffer.vhd" "" { Text "D:/my_eda/tri_bibuffer/tri_bibuffer.vhd" 4 -1 0 } } { "e:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "b\[4\]" } } } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { b[4] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { b[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional b\[3\] 3.3-V LVTTL " "Info: Type bidirectional pin b\[3\] uses the 3.3-V LVTTL I/O standard" {  } { { "tri_bibuffer.vhd" "" { Text "D:/my_eda/tri_bibuffer/tri_bibuffer.vhd" 4 -1 0 } } { "e:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "b\[3\]" } } } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { b[3] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { b[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional b\[7\] 3.3-V LVTTL " "Info: Type bidirectional pin b\[7\] uses the 3.3-V LVTTL I/O standard" {  } { { "tri_bibuffer.vhd" "" { Text "D:/my_eda/tri_bibuffer/tri_bibuffer.vhd" 4 -1 0 } } { "e:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "b\[7\]" } } } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { b[7] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { b[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional b\[2\] 3.3-V LVTTL " "Info: Type bidirectional pin b\[2\] uses the 3.3-V LVTTL I/O standard" {  } { { "tri_bibuffer.vhd" "" { Text "D:/my_eda/tri_bibuffer/tri_bibuffer.vhd" 4 -1 0 } } { "e:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "b\[2\]" } } } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { b[2] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { b[2] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional b\[6\] 3.3-V LVTTL " "Info: Type bidirectional pin b\[6\] uses the 3.3-V LVTTL I/O standard" {  } { { "tri_bibuffer.vhd" "" { Text "D:/my_eda/tri_bibuffer/tri_bibuffer.vhd" 4 -1 0 } } { "e:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "b\[6\]" } } } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { b[6] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { b[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional b\[1\] 3.3-V LVTTL " "Info: Type bidirectional pin b\[1\] uses the 3.3-V LVTTL I/O standard" {  } { { "tri_bibuffer.vhd" "" { Text "D:/my_eda/tri_bibuffer/tri_bibuffer.vhd" 4 -1 0 } } { "e:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "b\[1\]" } } } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { b[1] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { b[1] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional b\[5\] 3.3-V LVTTL " "Info: Type bidirectional pin b\[5\] uses the 3.3-V LVTTL I/O standard" {  } { { "tri_bibuffer.vhd" "" { Text "D:/my_eda/tri_bibuffer/tri_bibuffer.vhd" 4 -1 0 } } { "e:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "b\[5\]" } } } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { b[5] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { b[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0 "" 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/my_eda/tri_bibuffer/tri_bibuffer.fit.smsg " "Info: Generated suppressed messages file D:/my_eda/tri_bibuffer/tri_bibuffer.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "188 " "Info: Allocated 188 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 20 15:47:14 2007 " "Info: Processing ended: Sun May 20 15:47:14 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:36 " "Info: Elapsed time: 00:00:36" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}