📄 tri_bibuffer.tan.rpt
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Classic Timing Analyzer report for tri_bibuffer
Thu May 31 09:55:22 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 10.505 ns ; a[5] ; b[5] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C8T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 10.505 ns ; a[6] ; b[6] ;
; N/A ; None ; 10.505 ns ; a[5] ; b[5] ;
; N/A ; None ; 10.497 ns ; a[0] ; b[0] ;
; N/A ; None ; 10.486 ns ; a[2] ; b[2] ;
; N/A ; None ; 10.483 ns ; a[1] ; b[1] ;
; N/A ; None ; 10.474 ns ; b[1] ; a[1] ;
; N/A ; None ; 10.446 ns ; b[0] ; a[0] ;
; N/A ; None ; 10.443 ns ; b[2] ; a[2] ;
; N/A ; None ; 10.435 ns ; b[5] ; a[5] ;
; N/A ; None ; 10.421 ns ; b[6] ; a[6] ;
; N/A ; None ; 10.410 ns ; b[3] ; a[3] ;
; N/A ; None ; 10.039 ns ; a[3] ; b[3] ;
; N/A ; None ; 9.183 ns ; a[7] ; b[7] ;
; N/A ; None ; 9.183 ns ; b[4] ; a[4] ;
; N/A ; None ; 9.182 ns ; a[4] ; b[4] ;
; N/A ; None ; 9.173 ns ; b[7] ; a[7] ;
; N/A ; None ; 8.140 ns ; en ; b[1] ;
; N/A ; None ; 8.130 ns ; en ; b[6] ;
; N/A ; None ; 7.897 ns ; en ; a[6] ;
; N/A ; None ; 7.873 ns ; en ; a[5] ;
; N/A ; None ; 7.843 ns ; dr ; b[1] ;
; N/A ; None ; 7.833 ns ; dr ; b[6] ;
; N/A ; None ; 7.792 ns ; en ; a[0] ;
; N/A ; None ; 7.562 ns ; dr ; a[6] ;
; N/A ; None ; 7.538 ns ; dr ; a[5] ;
; N/A ; None ; 7.536 ns ; en ; a[1] ;
; N/A ; None ; 7.526 ns ; en ; a[2] ;
; N/A ; None ; 7.458 ns ; en ; b[5] ;
; N/A ; None ; 7.458 ns ; en ; b[2] ;
; N/A ; None ; 7.457 ns ; dr ; a[0] ;
; N/A ; None ; 7.428 ns ; en ; b[3] ;
; N/A ; None ; 7.201 ns ; dr ; a[1] ;
; N/A ; None ; 7.191 ns ; dr ; a[2] ;
; N/A ; None ; 7.161 ns ; dr ; b[5] ;
; N/A ; None ; 7.161 ns ; dr ; b[2] ;
; N/A ; None ; 7.131 ns ; dr ; b[3] ;
; N/A ; None ; 7.100 ns ; en ; b[0] ;
; N/A ; None ; 7.096 ns ; en ; a[3] ;
; N/A ; None ; 6.803 ns ; dr ; b[0] ;
; N/A ; None ; 6.761 ns ; dr ; a[3] ;
; N/A ; None ; 6.246 ns ; en ; a[4] ;
; N/A ; None ; 6.196 ns ; en ; b[7] ;
; N/A ; None ; 6.145 ns ; en ; b[4] ;
; N/A ; None ; 6.115 ns ; en ; a[7] ;
; N/A ; None ; 5.911 ns ; dr ; a[4] ;
; N/A ; None ; 5.899 ns ; dr ; b[7] ;
; N/A ; None ; 5.848 ns ; dr ; b[4] ;
; N/A ; None ; 5.780 ns ; dr ; a[7] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Processing started: Thu May 31 09:55:20 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off tri_bibuffer -c tri_bibuffer --timing_analysis_only
Info: Longest tpd from source pin "a[6]" to destination pin "b[6]" is 10.505 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_71; Fanout = 1; PIN Node = 'a[6]'
Info: 2: + IC(0.000 ns) + CELL(0.954 ns) = 0.954 ns; Loc. = IOC_X32_Y0_N1; Fanout = 1; COMB Node = 'a[6]~1'
Info: 3: + IC(6.325 ns) + CELL(3.226 ns) = 10.505 ns; Loc. = PIN_69; Fanout = 0; PIN Node = 'b[6]'
Info: Total cell delay = 4.180 ns ( 39.79 % )
Info: Total interconnect delay = 6.325 ns ( 60.21 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
Info: Allocated 110 megabytes of memory during processing
Info: Processing ended: Thu May 31 09:55:22 2007
Info: Elapsed time: 00:00:02
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