tri_bibuffer.vhd

大量VHDL写的数字系统设计有用实例达到

library ieee;
use ieee.std_logic_1164.all;
entity tri_bibuffer is
port(a,b:inout std_logic_vector(7 downto 0);
     en:in std_logic;
     dr:in std_logic);
end;
architecture one of tri_bibuffer is
	signal a_out,b_out:std_logic_vector(7 downto 0);
begin
process(a,b_out,en,dr)
begin
	if en='1' and dr='1' then b_out<=a;
	else b_out<="ZZZZZZZZ";
	end if;
	b<=b_out;
end process;
process(a_out,b,en,dr)
begin
	if en='1' and dr='0' then a_out<=b;
	else a_out<="ZZZZZZZZ";
	end if;
	a<=a_out;
end process;
end;